Performance

All the RISC-V cores were benchmarked with a benchmark suite CHStone [41] that does not have benchmarks with floating point computation. The source code was compiled with RISC-V GNU Compiler Toolchain [42] version 11.1.0 that was configured to the RV32IM subset of the RISC-V ISA. JPEG as well as the double precision benchmarks were left out because they were too large for Pulpino’s 32kB memories.

The cycle count comparisons are presented in Figure 5.4. The generated cores with bypass support achieve significantly better cycle counts than the two reference cores.

The three-stage configuration has approximately 28% and 16% lower cycle counts than zero-riscy and RI5CY on average. The configuration with four pipeline stages suffers an overhead from the higher control flow latencies and achieves only 24% and 12% lower clock cycles compared to zero-riscy and RI5CY. The effect of missing bypasses can be seen in the cycle count results of the configuration with no bypass support that has on average 11% higher cycle counts than zero-riscy and 56% higher than the three-stage version with bypass support. The bypass connectivity is a very useful feature as it has only a minimal effect on the synthesis results while lowering the cycle counts significantly.

However, the RI5CY core suffers a significant overhead from the missing forwarding sup-port from the load-store unit, causing a 22% overhead on average. Zero-riscy suffered even larger overhead due to the multi-cycle memory operations where both load and stores take the minimum of two cycles to complete. The overhead of the stalls caused by memory operations in zero-riscy’s case was 47% in average.

Additional distortion in the results is caused by the differences in the division and remain-der operations that are implemented with dynamic latencies in the PULP-based refer-ence cores. However, these are relatively rare operations in the used benchmarks and only used in the aes benchmark where they make approximately 0.2% of all executed instructions. The mulh operations was not used in the benchmarks.

If the stalls caused by the load-store unit are discarded, the configuration with three pipeline stages and bypass support has 5% and 2% higher cycle counts compared to zero-riscy and RI5CY. Zero-riscy can handle control-oriented code with less penalty due to its less aggressive pipelining. The overhead caused by the missing flush support can be seen in the control heavy mips benchmark where not taken branches make 3.5% of all instructions. In this scenario, the configuration with three pipeline stages and bypass support has 11% and 6% higher cycle counts than zero-riscy and RI5CY if the load-store unit caused stalls are removed. Even though the two generated cores are able to achieve low cycle counts due to their memory interface and bypass connectivity, the evaluated penalty of control flow operations adds motivation for future flush support.

Run time of the benchmarks described in Figure 5.5 can be extracted by combining the clock cycle counts presented in Figure 5.4 with the maximum clock frequencies presented in Figure 5.2. The configuration with three pipeline stages and bypass support achieves the lowest run time of the designs because of its higher clock frequency, offering in aver-age 41% and 48% lower run time than zero-riscy and RI5CY. Even when the load-store unit caused stalls are removed from the run time, the cores’s run time is 13% and 37%

lower than zero-riscy’s and RI5CY’s. The configuration with four pipeline stages achieved 8% and 34% lower run time when the load-store unit induced stalls were discarded.

Overall, the reference cores and the configuration with three pipeline stages and bypass support achieved similar clock cycle counts when the LSU induced stalls were discarded

adpcm aes blowfish

Figure 5.4.Cycle counts compared to zero-riscy baseline

adpcm aes blowfish

Figure 5.5.Run time compared to zero-riscy baseline

from the results of the reference cores. This is due to the similar operation latencies be-tween the cores, which proves that using a TTA core as the internal microarchitecture to implement the RISC-V ISA can provide competitive results, even providing significantly faster run times than the two reference implementations. The configuration without by-pass connectivity experiences significant overhead due to the missing operand forwarding support, which emphasises the importance of bypass connectivity. The configuration with an extra pipeline stage could not achieve better performance as it had higher control flow latencies and same clock frequency as the three pipeline stage version. Better clock fre-quencies could be achieved if the register file read was made synchronous or registers were added to the function unit input ports. If the register read were synchronous, the mi-crocode would need a more complex sequencer as the micro-operations would need to be sequenced in three cycles instead of two as in the current implementation. Registers in the function unit input ports would effectively raise the operation latency to two clock cycles. It could, however, be trivially pipelined, but that would cause problems with data forwarding as it has a similar effect to separating the memory access to its own stage where even a forwarded operand would cause a stall during a data hazard.