IGBT module failure mechanisms caused by thermal loading

In principle, thermal loading is affected by two main factors (Ma et al., 2015). First, the power device operates at a specific load current, switching frequency, modulation index, power factor, and DC link voltage. Thus, dynamic electrical loading induces power loss dissipation in the module and causes junction temperature fluctuations. Another factor

affecting thermal loading is the device rating. High current and voltage ratings of the semiconductor significantly increase the power loss (Roshanfekr et al., 2012), (Ma et al., 2015). Hence, in (Roshanfekr et al., 2012) it was reported that a power loss increase in the converter reached 67 % with IGBT modules of a rated voltage of 6.5 kV instead of 1.7 kV.

It is pointed out that the power loss generation and the reliability performance are highly dependent on the IGBT technology. In a low-voltage system with a high switching frequency, as in this research, an IGBT module and the IGBT press-pack topology are preferred (Senturk, 2011). The press-pack technology has a more rigid structure, achieved by the individual spring-contacted chips (Figure 1.3) and by avoiding the bond wires and solder joints, as in the IGBT module. In Figure 1.3, the silicon (Si) chips are enclosed between the conductive top and base plates. The contact piston presses the top plate and the chip against the base plate. The structure is held together between the module housing power connections and the electrically isolated housing element (Gunturi

& Schneider, 2009). The CTE of the top and bottom base plates is close to or matches that of the silicon chips.

Figure 1.3: Press-pack IGBT submodule structure (Gunturi & Schneider, 2009)

However, the IGBT module topology has less mounting arrangement and is cheaper than the press-pack IGBT. The IGBT module also has a longer track record of application and is still dominant in high-power applications (Ma & Blaabjerg, 2012). Thus, in the present research, the IGBT module is considered. The package-related failures, associated with different thermal properties of the materials used in the module, are discussed.

In Figure 1.4, the cross-sectional structure of the IGBT module is presented. The Si chips are connected with aluminium (Al) bond wires through an Al metallization layer (not shown in the figure). The chips are soldered on a copper (Cu) layer, which forms the IGBT circuitry pattern. A ceramic substrate, made of aluminium oxide (Al2O3) or aluminium nitride (AlN), with bonded copper on the both sides forms the direct copper-bonded (DCB) substrate. The ceramic substrate provides an electrical isolation, and the copper layers decrease the thermal resistance of the device (Ikonen, 2012). The copper base plate is soldered to the DCB substrate. Local temperature fluctuations between the layers cause thermo-mechanical fatigue stress as a result of the continuing expansion and

contraction of the material. In Table 1.2, the CTEs of the materials typically used in the IGBT module are presented (Khanna, 2003).

Figure 1.4: Structure of the IGBT module.

Table 1.2: Coefficients of thermal expansion (CTE) of the materials typically used in the IGBT module (Khanna, 2003).

Material Symbol CTE

(ppm/K) Function

Silicon Si 2.6 Material for IGBT chip fabrication

Aluminium Al 23 Bond wires and metallization

Aluminium oxide Al2O3 10.7 Substrate material Aluminium

nitride

AlN 3.1 Substrate material

Copper Cu 16 Base plate

Thermal grease – 0.4-1 Thermal contact between base plate and heat sink

The greatest mismatch in the CTEs of the two stack materials is between the Al bond wires and metallization and the silicon chips. The CTE of aluminium (23 ppm/K) is about nine times that of silicon (2.6 ppm/K), in other words, aluminium expands more than silicon. Thus, the bonded interface between the layers is exposed to the propagation of fractures. Moreover, high temperature fluctuations result in reconstruction of the Al metallization layer. Finally, the resultant degradation of the contacting areas caused by crack propagation leads to bond wire lift-off (Ciappa, 2002) (Figure 1.5).

Figure 1.5: Heal cracking and trace of a lifted bond wire of a diode (Amro & Lutz, 2004).

Usually, multiple bond wires are positioned in parallel on the chip in order to relieve the current load and prevent excessive ohmic heating. Under normal operating conditions, the maximum current capability of a single Al wire is 10 A (Ciappa, 2002). The bond wire, which has lost connection with the chip, induces additional current load in the normally operating wires. Thus, the current will be uniformly distributed among the other bond wires. However, after the bond wire lift-off, the temperature distribution over the chip will not be uniform. The non-uniform temperature distribution induces further bond wire breakage. According to (Chen et al., 2012), the bond wires continue to fail from the centre of the chip to the edges.

Methods to improve the bond wire connection are discussed in (Ciappa, 2002). These are application of a molybdenum-aluminium (Mo-Al) layer between the Si chip and the bond wire in order to improve distribution of the mismatch in the CTEs, and covering the bond wire with polymeric coating to eliminate physical separation of the bond wire feet from the chip.

The difference in the CTEs of the silicon chip and the copper substrate also leads to deformation of the bonding interface (CTEs 2.6 and 16 ppm/K). Here, formation of voids and cracks occurs in the solder interface between the silicon chip and the copper base plate. The same degradation mechanism takes place in the solder layer between the ceramic substrate and the copper base plate (CTEs 5.5 (Al2O3) and 16 ppm/K). In particular, crack formation occurs from the periphery to the central region of the solder layer (Figure 1.6) as a result of a higher shear stress on the edges of the solder interface (Ciappa, 2002). After the solder delamination has started, the ageing process accelerates as a result of the increase in the thermal resistance and the temperature difference in the module.

Figure 1.6: Solder degradation (bright areas), delamination of the layer starting from the corners towards the centres (Perpiñà et al., 2012).

The most critical solder connection is found between the ceramic substrate (Al2O3) and the Cu base plate because of its large lateral size. The reliability of the solder joints can be improved by reducing the areas of attachments, and therefore, the DCB is often divided into several parts. Thus, the connection of the copper base plate and the DCB could be improved by reducing the average difference in thermal expansions (Wintrich et al., 2015). Additionally, it is possible to increase the thickness of the solder, thereby reducing the material stress on the edges (Ciappa, 2002). Combination of the AlN substrate and the AlSiC base plate would give better matching between CTEs. Moreover, the AlN substrate is the best combination with silicon chips (Wintrich et al., 2015).