7. Conclusions
7.2 Future Development
There is room for improvement and further research in various areas of this work.
First, some other mechanisms can be added to get rid of the external overheads. One is the adoption of a FIFO-like control memory.
CREMA presents interesting research opportunities. Augmenting the flexibility of the template we can significantly extend the application range. For example, adding the support for arithmetic in Galois-field can allow the usage for encryption algo-rithms. The possibility to use a variable data width for different PEs should also be explored. All of these modifications would act on the template without increasing the implementation costs of a specific instantiation of CREMA.
The programming flow can also be improved through adding automatic features to help the application developer, thus reducing the development time. In particular, the programming flow could be extended to a larger range of architectures based on same principles (a processor tightly-coupled with an accelerator).
Finally, the mapping adaptiveness used in CREMA can be applied in a wider scope that extends it to fine-grain architectures. Considering for example a FPGA, one could think of customizing its architecture to the application requirements. This means that we would no longer have a homogeneous array of LUT-based logic blocks.
Each block could have different characteristics (size of the LUT, interconnections) that are fixed according to the application implemented on it. Such a customized FPGA cannot be used anymore for prototyping purposes or as a fast development platform because of its reduced flexibility. However, it can serve as a dedicated ac-celerator that can support a limited number of applications (e.g. FFT, FIR or corre-lations), and the customer decides on-the-field which one of the provided functional-ities he wants to use. Such a dedicated FPGA would have a market narrower than a standard FPGA chip and thus could be a bit more expensive although its development costs could still be less than an ASIC implementation. In addition, it could guaran-tee better performance and energy efficiency than a general-purpose FPGA. Future research is needed to evaluate the real potential of this approach.
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