• Ei tuloksia

5 EVALUATION & CONCLUSION

This chapter evaluates and concludes the test results. It also summarizes the methodolo-gies and characteristics that are useful when measuring time synchronization accuracy.

The reasons that are causing the inaccuracies to time synchronization are also summa-rized in this chapter.

For measuring time synchronization the traditional way is the 1PPS method which is sim-ple to imsim-plement especially in laboratory environments. However, this is not convenient in large scale networks. Ingres, egress and reverse sync methods are however better op-tion for larger networks because they use in-band reporting method and the calculaop-tions are done by slave or master.

When measuring or monitoring the time synchronization accuracy, the most important characteristics that should be measured are Maximum Time Interval Error (MTIE), Time deviation (TDEV) and Mean Path Delay. MTIE clarifies the highest offset peak between synchronized devices. TDEV defines the stability between a measured phase to a refer-ence phase. Mean Path Delay defines the average time of the link between master and slave.

There are various factors that have and impact to the time synchronization accuracy. The common reasons that are causing the time errors in time synchronization process are listed below:

• Clock frequency

• Quality and stability of an oscillator

• Propagation delays at PHY

From these, the performed test cases verified the enviromental changes, stability of an oscillator, propagation delays and traffic. These are the factors that should be taken in consideration then developing an Ethernet device for synchronous network.

This will ease the costs and the effort of the development of a PTP capable industrial network device. With the right architectural choices, the development of such devices would be more cost efficient and the device itself becomes more durable.

Overall the DUT used in this thesis achieved its goals to maintain the time synchroniza-tion accuracy below 1 µs. These test gives the rough estimate how the device behaves in different situations. Summary of the test results are presented in Figure 5.1 and Fig-ure 5.2. The FigFig-ure 5.1 presents the average offsets and the FigFig-ure 5.2 presents the average mean path delays from every test case.

Figure 5.1. MTIE and Average Offset results

Figure 5.1 shows that there are no remarkable differencies between average offsets ex-ecpt with the high load traffic test. That is the one that is approximately 5nshigher than other test cases. The high load traffic case is also above others when comparing the MTIE results. Long data path increases also the time error noticeably.

Figure 5.2.Average Mean Path Delay results

Based on these results it is important to take the traffic controlling in consideration if the device will handle heavy traffic. This will cause some inaccuracies in the time synchro-nization. Also, when creating an industrial network it is important to take in consideration the length and topology of the data path. Long data paths will cause minor inaccuracies in time and it will also increase significantly the path delay as shown in Figure 5.2.

The overall average path delays were not impacted almost at all excluding the long dat-apath test. In conclusion, only longer data paths have an effect on the mean path delay based on these tests.

Another useful test case for measuring the time synchronization is testing with different oscillators. With different oscillators, the enviromental changes are playing a bigger role.

Especially if the oscillator is a low-end model and it has no thermal controlling, it might be affected easily by the temperature or humidity changes. In this case the DUT had a good quality oscillator which was not affected that much from the enviromental changes.

The test setup which included the Calnex Paragon device (Figure 3.7) is a useful setup for creating various test cases. Unfortunately, the test setup did have some functional diffuculties thus some important test cases were not feasible to execute. Test case such as creating asymmetric data path is a great test for accuracy testing because the PTP relies on a symmetric data path. Another helpful test case is a test where the resolution of the timestamp is decreased which will reduce the precision of the time calculations.

Third useful test case with the Calnex testing device is a test where jitter, wander and broken packets are generated to the test network for creating disturbance to the time synchronization calculations.

REFERENCES

[1] S. Hampton. 5 Essential Elements of Network Time Synchronization. (Aug. 2018).

URL: https://www.microsemi.com/document-portal/doc_download/133205-5-essential-elements-of-network-time-syncronization.

[2] S. Bregni. Synchronization of Digital Telecommunications Networks. Mar. 2002.

DOI:10.1002/0470845880.

[3] IEEE Standard for Ethernet. IEEE Std 2015 (Revision of IEEE Std 802.3-2012)(Sept. 2015), 1–4017.

[4] Phoenix Contact, Ethernet Basics Rev. 02. URL: https : / / www . mouser . com / pdfdocs/Ethernet_Basics_rev2_en.pdf.

[5] Dinh Thai Bui and M. Le Pallec. From Ethernet to Synchronous Ethernet.2008 2nd International Conference on Signal Processing and Communication Systems. Dec.

2008, 1–5.DOI:10.1109/ICSPCS.2008.4813737.

[6] M. Henderson and T. Shaver. Sampling synchronization with Gigabit Ethernet.

OCEANS 2009. Oct. 2009, 1–7.DOI:10.23919/OCEANS.2009.5422060.

[7] N. Kerö, A. Puhm, T. Kernen and A. Mroczkowski. Performance and Reliability As-pects of Clock Synchronization Techniques for Industrial Automation.Proceedings of the IEEE 107.6 (June 2019), 1011–1026.DOI:10.1109/JPROC.2019.2915972. [8] A. Dobrogowski, M. Jessa, M. Kasznia, K. Lange and M. Jaworski. Hardware and

software realization of time error measurements with real-time assessment of ADEV, TDEV, and MTIE. EFTF-2010 24th European Frequency and Time Forum. Apr.

2010, 1–8.DOI:10.1109/EFTF.2010.6533710.

[9] S. Bregni. Measurement of maximum time interval error for telecommunications clock stability characterization. IEEE Transactions on Instrumentation and Mea-surement 45.5 (Oct. 1996), 900–906.DOI:10.1109/19.536708.

[10] S. Bregni and P. Tavella. Estimation of the percentile maximum time interval error of Gaussian white phase noise.Proceedings of ICC’97 - International Conference on Communications. Vol. 3. June 1997, 1597–1601 vol.3.DOI:10.1109/ICC.1997.

595057.

[11] A. Dobrogowski and M. Kasznia. Real-time Assessment of Allan Deviation and Time Deviation.2007 IEEE International Frequency Control Symposium Joint with the 21st European Frequency and Time Forum. May 2007, 877–882.DOI:10.1109/

FREQ.2007.4319204.

[12] M. A. Weiss and K. Shenoi. The Time Deviation in Packet-Based Synchronization.

IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control63.4 (Apr.

2016), 531–537.DOI:10.1109/TUFFC.2015.2495011.

[13] A. Dobrogowski and M. Kasznia. Joint real-time computation of Allan deviation, time deviation, and Hadamard deviation. EFTF-2010 24th European Frequency and Time Forum. Apr. 2010, 1–7.DOI:10.1109/EFTF.2010.6533709.

[14] 802.1AS Recovered Clock Quality Testing. Rev. 1.0 (Oct. 2013). URL: https://

avnu.org/wp-content/uploads/2014/05/Avnu-Testability-802.1AS-Recovered-Clock-Quality-Measurement-1.0_Approved-for-Public-Release.pdf.

[15] K. Zhou, Y. Han and J. Tao. Timing synchronization using 1PPS for crosswell elec-tromagnetic logging tools.2017 Chinese Automation Congress (CAC). Oct. 2017, 316–319.DOI:10.1109/CAC.2017.8242784.

[16] F. Gardner.Phaselock Techniques. Vol. Third Edition. 2005, 209–236.

[17] Selecting Oscillator Technology. Precise Time and Frequency, Inc. (2015). URL: http://www.ptfinc.com/wp-content/uploads/2015/10/Selecting-Oscillator-Technologies.pdf.

[18] T. Yamashita and S. Ono. A statistical method for time synchronization of com-puter clocks with precisely frequency-synchronized oscillators. Proceedings. 18th International Conference on Distributed Computing Systems (Cat. No.98CB36183).

May 1998, 32–39.DOI:10.1109/ICDCS.1998.679484.

[19] J. Vig. Introduction to Quartz Frequency Standards. Army Research Laboratory, Electronics and Power Sources DirectorateRev. 1 (Oct. 1992). URL:http://www.

oscilent.com/esupport/TechSupport/ReviewPapers/IntroQuartz/vigtoc.htm. [20] C. Yong, W. Hao, T. Xiaofeng and W. Wenbo. Clock synchronization technology

based on FPGA.2015 IEEE International Conference on Communication Software and Networks (ICCSN). June 2015, 43–46.DOI:10.1109/ICCSN.2015.7296124. [21] P. Ruiqing, H. Peng, Y. Wenxue, G. Min and Z. Bin. The optimization techniques for

time synchronization based on NTP.2010 2nd International Conference on Future Computer and Communication. Vol. 2. May 2010, V2-296-V2–299.DOI:10.1109/

ICFCC.2010.5497413.

[22] D. L. Mills. The Network Time Protocol.Computer Network Time Synchronization.

2006.

[23] L. Zhang, Z. Liu and C. Xia. Clock synchronization algorithms for network measure-ments. Proceedings.Twenty-First Annual Joint Conference of the IEEE Computer and Communications Societies. Vol. 1. Feb. 2002, 160–169 vol.1. ISBN: 0-7803-7476-2.DOI:10.1109/INFCOM.2002.1019257.

[24] P. D. D. Heffernan. Time-triggered Ethernet based on IEEE 1588 clock synchroni-sation.Assembly Automation. Vol. 24. 3. 2004, 264–269.DOI:https://doi.org/

10.1108/01445150410549755.

[25] D. Rosselot. Simple, Accurate Time Synchronization in an Ethernet Physical Layer Device. 2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication. Oct. 2007, 123–127.DOI:10.1109/

ISPCS.2007.4383785.

[26] IEEE Standard for a Precision Clock Synchronization Protocol for Networked Mea-surement and Control Systems.IEEE Std 2008 (Revision of IEEE Std 1588-2002)(July 2008), 1–300.DOI:10.1109/IEEESTD.2008.4579760.

[27] A. O. Alshaikhli and J. M. Rhee. TFR: A Novel Approach for Clock Synchronization Fault Recovery in Precision Time Protocol (PTP) Networks.Applied Sciences 8.1 (2017).ISSN: 2076-3417.URL:http://www.mdpi.com/2076-3417/8/1/21.

[28] L. Xie, Y. Wu and J. Wang. Efficient time synchronization of 1588v2 technology in packet network.2011 IEEE 3rd International Conference on Communication Soft-ware and Networks. May 2011, 181–185.DOI:10.1109/ICCSN.2011.6014030. [29] H. Weibel. High precision clock synchronization according to IEEE 1588

implemen-tation and performance issues.Proc. Embedded World, 2005. Jan. 2005.

[30] Y. Jeon, J. Lee and S. Park. An efficient method of reselecting Grand Master in IEEE 802.1AS.The 20th Asia-Pacific Conference on Communication (APCC2014). Oct.

2014, 303–308.DOI:10.1109/APCC.2014.7091652.

[31] Ixia.Measuring 802.1AS Slave Clock Accuracy.URL:https://www.ixiacom.com/

resources/measuring-8021as-slave-clock-accuracy.

[32] M. H. Farzaneh and A. Knoll. Time-sensitive networking (TSN): An experimental setup.2017 IEEE Vehicular Networking Conference (VNC). Nov. 2017, 23–26.DOI: 10.1109/VNC.2017.8275648.

[33] Time-Sensitive Networking (TSN) Task Group. URL: https://1.ieee802.org/

tsn/.

[34] A. Regev. Measuring 802.1AS Slave Clock Accuracy. URL:https://standards.

ieee.org/content/dam/ieee-standards/standards/web/documents/presentations/

d2-06_regev_measuring_slave_clock_accuracy_v3.pdf.

[35] Network Cable Propagation Delay. URL: https : / / www . flukenetworks . com / knowledge-base/dtx-cableanalyzer/propagation-delay.