Muon Detector Link System Test Setup Software

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MUON DETECTOR LINK SYSTEM TEST SETUP SOFTWARE

The topic of the Master’s thesis has been approved by the department council of the De- partment of Electrical Engineering on 15th November 2006.

The supervisors and examiners of the thesis are Professor Tuure Tuuva and Professor Matti Alatalo.

Lappeenranta 2006-11-17 Ville Vehmaa

Huhtiniemenkatu 15 A 17 53810 Lappeenranta Tel. 044 348 0686

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Author: Vehmaa, Ville

Subject: Muon detector link system test setup software Department: Department of electrical engineering

Year: 2006

Place: Lappeenranta

Lappeenranta University of Technology. 32 pages, 12 figures, 2 tables and 1 appendix.

Supervisor: Professor Tuure Tuuva and professor Matti Alatalo Keywords: CMS, RPC, muon

The CMS experiment station of the LHC particle collider under construction at CERN will be dedicated for muon detection. In this work the link system of the RPC detector of CMS experiment and devices designed for testing the link system are presented. Also presented are software needed for link system testing. In this work the functionality and mutual compatibility of the software is described.

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Tekijä: Vehmaa, Ville

Työn nimi: Myoni-ilmaisimen linkkijärjestelmän testiympäristön ohjelmistot Osasto: Sähkötekniikan osasto

Vuosi: 2006

Paikka: Lappeenranta

Diplomityö. Lappeenrannan teknillinen yliopisto. 32 sivua, 12 kuvaa, 2 taulukkoa ja 1 liite.

Tarkastajat: Professori Tuure Tuuva ja professori Matti Alatalo Hakusanat: CMS, RPC, muon

Euroopan hiukkastutkimuslaitoksen CERNin rakenteilla olevan LHC-hiukkaskiihdyttimen CMS-koeasema on tarkoitettu erityisesti myonin ilmaisuun. Tässä työssä on esitelty CMS-koeaseman RPC-ilmaisintyypin linkkijärjestelmä ja sen testaamiseen tarkoitetut lait- teet sekä laitteiden testaamiseen tarvittavat ohjelmistot. Työssä on selvitetty ohjelmien toimivuus ja keskinäinen yhteensopivuus.

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This Master’s thesis has been done as a part of the CERN project of Microelectronics laboratory at Lappeenranta University of Technology. This project has been succeeded in close cooperation with Warsaw University.

Thanks to professors Tuure Tuuva and Matti Alatalo for supervising. Also thanks to the staff of Lappeenranta University of Technology, Warsaw University, and CERN.

Special thanks to MSc. Antti Puisto and MSc. Vesa Väisänen. They have given me great support during my long studies.

Lappeenranta 2006-11-17

Ville Vehmaa

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Symbols and abbreviations

η Pseudorapidity, a measure of angle c Speed of light,c= 299 792 458m/s

E Energy

L Luminosity, the measure of the performance of an accelerator ASCII American Standard Code for Information Interchange

ALICE A Large Ion Collider Experiment ATLAS A Toroidal LHC ApparatuS CB Control Board

CCS Clock and Control System

CCU Communication and Control Unit CMS Compact Muon Solenoid

CP Charge Conjugation, Parity, a violation in physics CSC Cathode Strip Chamber

CVS Concurrent Versions System DAQ Data Acquisition

DARPA Defence Advanced Research Projects Agency

DCS Detector Control System, Distributed Control System ECAL The Electromagnetic Calorimeter

FEB Front End Board FED Front End Driver

FPGA Field Programmable Gate Array

GNU GNU’s Not UNIX, a project to develop free UNIX software GOL Gigabit Optical Link

GPL GNU General Public License HAL Hardware Access Library HCAL The Hadronic Calorimeter HTTP HyperText Transfer Protocol IC Integrated Circuit

JTAG Joint Test Action Group

L1 Level 1

LB Link Board

LEP The Large Electron Positron Collider LHC Large Hadron Collider

LHC-b Large Hadron Collider Beauty Experiment LVDS Low Voltage Differential Signalling

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mFEC mezzanine Front End Control PCI Peripheral Component Interconnect RPC Resistive-Plate Chamber

RPCT RPC Trigger

SLC Scientific Linux CERN

SM The Standard Model Of Particle Physics SOAP Simple Object Access Protocl

TTC Timing, Trigger and Control System TTCvi TTC interface to VME bus

TTCvx module for TTC encoding with four optical transmitters U A unit of height of 19 inch crate. U = 44.45mm

UNIX An operating system for computers VME VERSAmodule Eurocard

XDAQ DAQ software used at CERN XML Extensible Markup Language

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1 Preface

At Lappeenranta University of Technology (LUT) the Department of Electrical Engi- neering is designing the link and control boards needed for the Compact Muon Solenoid (CMS) experiment of the new particle accelerator at CERN. CERN is the European Or- ganization for Nuclear Research. It is located in Switzerland and France near the Swiss city of Geneva. It is also known for being the birthplace of the World Wide Web.

CERN is the world’s largest particle physics and high energy physics laboratory. High energy physics is studying the structure of matter. The device needed for high energy physics experiments is called a particle accelerator. The largest particle accelerator facility in the world is at CERN. The new particle accelerator, the Large Hadron Collider (LHC) is being built.

In the LHC one type of detector used to detect particles generated by the collisions is called a resistive-plate chamber. The data given by these detectors is transferred by a purpose-built Link Board. In this study I have examined the software needed for Link Board control and Link Board testing.

2 Standard Model of particle physics

The Standard Model of Particle Physics (SM) is a theory describing fundamental interactions (”forces”) and elementary particles. These fundamental interactions are weak, strong, electromagnetic and gravitational interactions. The elementary particles are di- vided into two groups: fermions and bosons. The groups of these particles are presented in figure 1.

All the matter—and antimatter—consists of fermions. There exists two groups of fermions:

leptons and quarks. Quarks are called as up, down, charm, strange, top and bottom.

Hadrons are particles made only from quarks. The best known hadrons are proton and neutron. Every fermion has it’s own antiparticle, which has the same mass, spin and isospin as fermion. Masses of the quarks are collected into table 2.

In particle physics the mass of a particle is measured by energy units. The conversion

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gluon µ tauτ electron e

νe electron neutrino

νµ muon neutrino

ντ tau neutrino Leptons

up down strange charm bottom top Quarks

Fermions

W+ W−

and Z 0 photon graviton Higgs Boson

Bosons

Elementary particles

muon

Figure 1: Elementary particles.

between the mass and energyE is defined by the Einstein’s equation

E =mc², (1)

wherem is the mass of the particle in kilograms and c = 299 792 458 m/s is the speed of light in vacuum. The Einstein’s equation gives the energy of the particle in joules.

However, joule is an enormous unit in scale of particle physics. Thus another energy unit, electronvolt (eV), is used. Joules are converted to electronvolts dividing by1.602 176 53· 10¹⁴. Often in the particle physics the abbreviationeV/c² is used instead of simple eV.

A well known elementary particle called electron e⁻ belongs to the group off leptons.

The other leptons are muon µ, tau τ, electron neutrino νǫ, muon neutrino νµ and tau neutrinoντ. Massm, life timeτ and mass of neutrinoνof leptons are shown in table 3.

The fundamental interaction is carried by a special particle called boson. The bosons in the SM are photon, W⁺ and W⁻ boson, Z⁰ boson, gluons and Higgs boson. The Higgs boson is predicted by the SM, but it is still unknown if it exists or not. One of the main reasons for building the new particle accelerator is to get the evidence of the existence of Higgs boson. All bosons have an integer spin. The spin of Higgs boson is zero.

Matter is made from fermions, but not all fermions are the bricks of everyday matter.

All ordinary matter is made of electrons, electron neutrinos, up and down quarks. The

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other leptons and quarks are not used for creating ordinary matter. For example, everyday matter can not contain any muons or taus as they are unstable particles as seen on table 3.

2.1 Fundamental interactions

Fundamental interaction is a mechanism by which elementary particles interact with each other. Fundamental interactions describe all the other non-fundamental physical phenomena and they can not be explained by any other interaction. Particles of matter do not directly interact with each other but rather by exchange of interaction carrier particles.

These particles carrying forces are called bosons and their spin is always an integer.

The SM gives us four fundamental interactions: weak nuclear force, strong nuclear force, electromagnetic force and gravitation. Weak force is carried by bosons W⁺, W⁻ and Z⁰. It often occurs in radioactive decay. Electromagnetic interaction is carried by photon.

Strong interaction is the force which binds quarks into subatomic particles called hadrons.

The well known hadrons are neutron and proton. Quarks are not free particles, they are always bound to groups. The strong interaction is carried by gluons. There exists eight gluons. Leptons do not have strong interaction.

Gravitation influences on heavenly bodies like stars and planets. It is the weakest of the fundamental interactions, but it’s range is the longest. Gravitation is believed to be carried by graviton, a force particle which is not yet found. The spin of graviton is 2.

Table 2: Masses of quarks.

quark mass

up 5MeV

down 8MeV

strange 150MeV charm 1.2GeV bottom 4.2GeV

top 178GeV

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Table 3: Specifications of leptons.

electron muon tau

mass 0.5MeV 106MeV 1777MeV

lifetime 6·10²⁴y 2·10⁻⁶s 3·10⁻¹³s mass of neutrino <3eV <0.2MeV <18MeV

3 LHC

The particle collider at CERN currently under construction is called Large Hadron Col- lider. The collider will be the largest in the world and it is build in the same underground tunnel as the former accelerator, The Large Electron Positron Collider (LEP). First exper- iments at LHC are scheduled to late 2007.

In circular accelerators there are two beams running in opposite directions. The particles in those beams are however not alone, they are traveling in bunches. The speed of a bunch is 11 245.5 revolutions per second. Every bunch will meet another, opposite direction bunch every 25 ns. This short period of time is called the bunch crossing rate. The bunch crossing rate is equal to 40 MHz, which is the frequency of the LHC clock.

The former collider LEP had four experiments: ALEPH, DELPHI, L3 and OPAL. The Higgs boson was not found in these experiments. The LHC will have four experiments:

ALICE (A Large Ion Collider Experiment), LHC-b (Large Hadron Collider Beauty Ex- periment), CMS (Compact Muon Solenoid) and ATLAS (A Toroidal LHC ApparatuS).

The CMS and ATLAS are general purpose detectors detecting decay in proton-proton collisions (energy of 14 TeV). The LHC-b detector is dedicated to the study of CP violation and other rare phenomena in the decays of heavy particles.

The experiment used for heavy lead ion collisions is ALICE. The aim is to study the physics of strongly interacting matter at extreme energy densities, where the formation of a new phase of matter, quark-gluon plasma is expected.

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3.1 CMS

The Compact Muon Solenoid is a general purpose high energy physics detector. It is designed to run at the highest luminosity at LHC. LuminosityLdescribes the performance of the accelerator and its equation is

L= nbN1N2frev

A , (2)

wherenbis number of bunches in one beam,Nithe number of particles in each beam,frev

the revolution frequency and Ais the cross section of the beam. The unit of luminosity is cm⁻²s⁻¹. [1, 2, 3]

The CMS detector has been optimized for the search of the Higgs boson over a mass range from 90 GeV to 1 TeV, but it will also detect all decay products originating from the proton-proton collisions. It is also possible to use the CMS and the ATLAS experiments for searching new vector bosons W and Z and for discovery potential for first-generation leptoquarks. [1, 2]

3.1.1 The CMS detector

The CMS detector is a very large device: it’s diameter is about 14 m and weight 12 000 tons.

The detector contains a super conducting magnet with 4 T field in a solenoidal volume of 6 m diameter and 12 m length. The schematics of the CMS detector is shown in figure 2 and muon travel in the CMS detector is presented in figure 3. [1]

The CMS detector can be divided into three main subsystems [1, 2]:

• Calorimeters are needed for triggering, measuring and identifying electrons, pho- tons and jets and to detect the missing energy for measuring escaping non-interacting particles such as neutrinos. Particles are stopped by the calorimeters for energy measurement. The first layer, the electromagnetic calorimeter (ECAL) will mea- sure the energy of electromagnetically interacting particles, electrons and photons.

The next layer, called the hadronic calorimeter (HCAL), is for hadron energy mea- surement. ECAL is made of lead tungstate PbWO4 crystals and HCAL is made of brass acting as the absorber while scintillator is used for active sampling.

• The tracking systems. The inner tracking detectors are designed to identificate and

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Compact Muon Solenoid

Pixel Detector Silicon Tracker Very-forward

Calorimeter

Electromagnetic Calorimeter Hadronic Calorimeter

Preshower

Muon Detectors Superconducting Solenoid

Figure 2: The CMS detector. [5]

measure high-ptmuons, electrons and hadrons with high momentum resolution and high efficiency in the range of pseudorapidity|η| <2.5. The pseudorapidityηis a measure of angle and is defined by

η = ln tanθ

2, (3)

whereθis the angle between the outgoing particle and the undeflected beam.

The most inner detectors are silicon pixel detectors with silicon surface of about 0.92 m². The second most inner detectors are silicon microstrip detectors with silicon area of about 198 m² which thus will be the largest silicon strip detector in the world.

• The muon system (spectrometer) has three main tasks: muon identification, muon trigger and muon momentum measurement. The muon system is divided in a barrel part (|η|<1.2) and endcap parts (0.9<|η|<2.4). Three different technologies are used to detect and to measure the muons: drift tubes in the barrel region, cathode strip chambers (CSCs) in the endcap region and resistive-plate chambers (RPCs) both in the barrel and in the endcap regions.

3.2 The CMS muon trigger

In the LHC two beams revolve around the accelerator tube in opposite directions crossing each other every 25 ns. It is believed that about 25 collision events occur at every bunch

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Figure 3: Muon running throught the CMS detector [5].

crossing for the normal LHC luminosity of 10³⁴cm⁻²s⁻¹. This gives us 1000 million events every second! The event rate needs to be reduced to 100 interesting events per second for storing all necessary event information. This amount of data can be analyzed by the computer grid. [1, 2]

The event reducing is a task of the CMS trigger and data acquisition system (TriDAS).

The reduction will be made in two phases by Level 1 (L1) trigger and high level trigger.

The CMS data acquisition (DAQ) has to read an event information and reconstruct it to an object which will be processed by the computer grid. Another task of DAQ is to monitor the detector elements. [1, 2]

The CMS L1 trigger has to make a decision of accepting a bunch crossing. This decision has to be made 40 million times per second. The L1 trigger is divided into three subsystems: the calorimeters trigger, the muon system and the global trigger. The task of the calorimeter and muon triggers is to identify and measure particles, the event selection is made by the global trigger. [1]

Between the L1 global trigger and the CMS readout and data acquisition system there is the trigger control system. Its main task is to control the delivery of the L1 Accept signal generated by the global trigger. [1]

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3.3 RPC front end electronics

The information from the RPC is delivered to the trigger system by the Front End Boards (FEB). The RPC readout strips are connected to the FEBs by kapton foils. Each FEB is handling 16 RPC channels. From FEBs the RPC signals are sent to the Link Boards (LB) for synchronization and data compression via low voltage differential signalling (LVDS).

Six FEBs are connected to a single LB. [1, 4]

The Front End Boards are not used in our test setup. The Link Board and its connection is described in chapter 4. Link Boards are controlled by the Distributed Control System (DCS). The general scheme of the Front End system is in figure 4. [6, 7]

TTC link

FEB FEB FEB FEB FEB FEB

LB

RPC Chamber

Figure 4: Data from the RPC Chamber is send to Link Boards through FEB cards. Six FEBs are connected to one Link Board.[4]

4 Test setup hardware

For testing Link Board prototypes, a test setup was build in the Laboratory of Microelec- tronics at LUT. In the test setup there were three main devices: a computer, a VME crate, and a link box. Test setup schematics is presented in figure 5.

4.1 VME control computer

A VME controller is required for connecting the computer to the VME crate. There has been three manufacturers for VME controller used at CERN: CAEN, National Instru- ments and SBS. All manufacturers are offering a PCI bus VME controller while CAEN

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A in B in A out B out DOH

I2C

CB LB

opt. in

Fanout opt. in opt. in

clock in

TTCvi

opt. out

out clock

TTCvx CAEN

V2718 FEC−

CCS VME Crate

opt. out

Test Pulse Board

fiber CAEN

A2818 Link Hardware

Linux

SLC XDAQ

FEC RPCT software DCS PC

Software

J T A G fiber

Figure 5: The block diagram of the test setup. In the drawing the test pulse board is connected via a cable to the link board; in reality it is attached directly to the back plane.

The Ethernet cable connecting the Control Board connector A(out) to the connector A(in) is not shown.

has also a USB device. For our test setup the CAEN V2818 PCI bridge and CAEN A2718 VME controller combination was chosen because they will be used in the final experiment.

4.2 VME crate

The VME crate in our test setup is a standard 19-inch crate containing four cards: the CAEN VME controller, TTCvi, TTCvx and FEC. The latest FEC card includes the functionality of CCS card—earlier the CCS card was separate and FEC was a PCI card inside a computer. The FEC card in our setup was a prototype version 2 and is developed by Kostas Kloukinas at CERN. Our FEC card had only one mFEC connector so it could be connected to only one link box.[7]

The height of a standard 19-inch crate is measured by units, or simple U. One unit is equal to44.45mm or1.75inch. The VME crate used in the CMS experiment is 9U of height.

In the crate only one card, FEC, is so high. All the other cards are 6U of height. The VME crate photo is in figure 6.

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Figure 6: VME crate used in our test setup.

4.3 Link box

All the electronics needed is not made with VME standard, so another crate is needed.

This crate is called link box. It is basically a 6U crate with 21 slots, rack cooling system, dedicated back plane and front plane.[8] The link box contains two kind of cards: the control board (CB) and the link board (LB). Additional MU module is also located inside the link box; it’s task is to divide the optical link from FEC to two CBs in the link box.

In our test setup the link box was an old style: it had an old-style CB and an old-style LB developed by Krzysztof Kierzkowski from Warsaw University. New cards will be designed by Electronics Design Center of LUT. The visible differences between the old and the new LB and CB are the physical size of the boards and different connectors. The photo of the mechanics of the final link box is presented in figure 7.

Every LB has an address for communication. As these addresses could be difficult to remember, those cards have got numbers easier for human communication. Numbers used for the nine LBs are 0–8, the card 0 is located next to the CB. The control computer has a file calledsystem.xmlwhich contains the explanation to the numbers. Thus it is easy to refer any link board without remembering addresses. Photo of old-style link box used in tests is shown in figure 8.

In the final experiment every link box contains one MU module, two CBs and 18 LBs—

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Figure 7: Mechanics of final link box.

nine LBs for each CB. Link boards are in six groups: each group has one master link board with optical output and two slave link boards without optical output. All the slave LB output will be send through the master LB.

All the cards are connected to a back plane and a front plane. In our test setup containing old style CBs and LB the TTC clock fiber from TTCvx card was connected to the front plane. In the future link box front plane is just a plane with connectors; it does not have any kinds of electronics. The task of the back plane is to distribute power to the all cards and leed through signals.

The control board IC has to be loaded for proper communication with FEC. In the CB there is a JTAG connector for this programming. The CB has to be programmed through JTAG every time the power is switched on.

4.4 Test pulse board

For test purposes a test pulse board was designed by Krzysztof Kierzkowski in Warsaw University. This simple board is connected to the link box back plane. It connects to the selected link board throught the back plane. In figure 5 this test pulse board is separated.

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Figure 8: Old-style link box used in tests. Link board slots are marked by red numbers.

In reality, it is located behind the link box.

The test pulse board is used to test the link boards’ ability to read, store and forward the data coming to the back plane connector. These tests are performed by sending LVDS level high signal to the back plane connectors. For reading the test pulse data a pulses.exeprogram is used. This program is developed by Michal Pietrusinski and Karol Bunkowski from Warsaw University and it is distributed with the RPCT software package.

4.5 Connection

All the hardware needs to be properly connected for proper working. The VME crate is connected to the computer via CAEN cards by optical fiber. The TTCvx card in the VME crate delivers the TTC clock signal to link box front plane. In the final link box the TTC clock input is in the control board, not anymore in the front plane.

Link box also needs to be connected to the CCU ring; thus an optical fiber is needed between the FEC and MU module. The purpose of the MU module is to distribute the TTC clock signal to both control boards in the link box. In the final experiment, the MU module will be located in the right end of the link box. Making the CCU ring active,

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two short and direct (i.e. not cross connected) Ethernet cables are needed: one cable is connected from CCU channel A output to channel A input and another from the channel B output to channel B input.

For loading the control board FPGA software a JTAG cable is needed. A cable used in our test setup is a typical JTAG cable connected to the parallel port of the PC. The control board FPGA loses its memory when power is switched off, so the programming has to be done at every boot.

5 Test setup software

5.1 SLC Linux

Linux is a free, GPL licensed Unix-type open source operating system. Its kernel is orig- inally designed by Linus Torvalds at University of Helsinki. An entire operating system based on Linux kernel is called a distribution. One of the most popular distributions is Red Hat Linux.

Linux kernel and many—if not all—components of Linux distributions are open source and GNU GPL (GNU General Public License) licensed. Open source means that the software source code is open for editing and changing to anyone. This makes the fast and reliable software development possible. The GPL license is a type of license created by Free Software Foundation and it ensures the freedom of software source code editing and distribution.

Scientific Linux is a distribution created by Fermilab, CERN and various other labs and universities around the world. It seems to be based on Red Hat Enterprise distribution although it is not officially told. SLC Linux distribution is Scientific Linux with CERN logo added. Virtually every Linux distribution could be used for our test setup, but the SLC Linux was chosen because it is widely used at CERN and at Warsaw University. [9]

A standard SLC Linux kernel was used. The performance of the 64 bit computer used in the test would be greatly improved if a 64 bit kernel was used. The standard 32 bit kernel was used to get as standard installation as possible.

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Although SLC Linux version 4 is available, the version 3 is still used. The next version, SLC5, will be used at LHC startup and most CERN services are expected to stay on SLC3 until then. [10]

5.2 XDAQ

Data acquisition (DAQ) is the sampling of the real world to generate data that can be manipulated by a computer. DAQ typically involves acquisition of signals and processing them to obtain desired information. [11]

A software product line called XDAQ (pronounced as crossdack) was designed for the development of distributed data acquisition systems. The XDAQ includes the generic requirements documents, design templates, a software process environment, a distributed processing environment and various generic software components that can be tailored to a variety of application scenarios. The overview of the XDAQ software package is presented in figure 9. In the figure the arrows indicate the work flow of the software process that leads to the production of DAQ systems and the extension of the product line asset base. [12]

XDAQ asset base

Product line requirements

Distributed processing environment

Generic application components

Configuration management infrasturcture

Customized DAQ System Production

prescriptions Newly created artifacts

Figure 9: Overview of the XDAQ software product line. [12]

The XDAQ software was developed at CERN. It is an open source project registered at SourceForge.net, which is the world’s largest open source software development web site

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hosting more than 100 000 projects. In the XDAQ development group there are eight developers including Johannes Gutleber, Luciano Orsini and Christoph Schwick. [13].

The XDAQ is designed for the data acquisition scenarios of the CMS experiment. These scenarios include the central DAQ, sub-detector local DAQ systems for commissioning, debugging, configuration, monitoring and calibration purposes, test-beam and detector production installations as well as design verification and demonstration purposes. [12]

A distributed processing environment is included into XDAQ providing functions for communication, configuration, control and monitoring. Configuration, control and monitoring can be done through the SOAP/HTTP protocol widely used in web applications.

The compiled XDAQ programs are loaded dynamically at run-time into a running execu- tive. [12]

5.3 CAEN driver

Every add-on card in the computer needs its own device driver for working properly. The CAEN V2718 PCI-to-VME bridge is not an exception. The driver versions 2.1 and 2.2 had compatibility problems with RPCT and FEC software so the newest version 2.3 had to be used. However version 2.3 is still not downloadable in the CAEN web page so it has to be downloaded from the CMS server.

5.3.1 Installing CAEN driver

The downloaded software package was unpacked. It was compiled by commandmake.

The device driver is loaded by running the scripta2818_load.

The device driver needs to be loaded every time when the computer is booted. This can be done manually after every boot by writing command

/usr/local/CAEN/CAEN-VME/Linux/driver/v2718/a2818_loadas user root. The device driver module can also be automatically loaded at every boot. First, the module has to be copied to kernel module directory. Copying can be performed for example by these commands:

export VERS=´uname -r´

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cp a2818.o /lib/modules/$VERS/misc/

chmod a+x /lib/modules/$VERS/misc/a2818.o

Then it is only needed to add the module loading command to the sysinit file. Add line /sbin/modprobe a2818 to file/etc/rc.d/rc.sysinit. Reboot the system, and thea2818device driver module should be loaded!

Even if the driver is loaded automatically during the boot, it is necessary to run the script once after installing CAEN drivers. The script does not only load the driver, it also creates the device files needed for device access. These device files must be created, otherwise the PCI bridge cannot be used!

5.4 HAL

HAL is a high level interface for user friendly hardware access to VME or PCI modules.

It is written by Christoph Schwick at CERN. HAL contains a software layer between the user program and the driver software to access the hardware. The HAL software is needed for compiling all the software—also FEC and RPCT—accessing to FEC card.

The present version of HAL is 03-09. All software used in our test setup is compatible with the present version of HAL. Earlier there were many compatibility problems; for example the RPCT software dated 2005-11-11 needed HAL version 03-07 and the FEC software was not compatible with it. HAL works only on Linux operating system. The reason for this is that Linux is the only operating system used in CMS experiment.

A class called BusAdapter implements the interface to hardware drivers. These drivers are included in the HAL package or can be written by the user. The HAL version installed by installFEC.shscript contained drivers for CAEN and SBS bridges. The driver does the actual access to the hardware and HAL is only a layer between the driver and software. The HAL blocks are presented in figure 10.

The HAL has been developed for the online environment of the CMS experiment at LHC.

In order to design and build a hardware module which is controlled by a computer, a lot of time is spent to develop the necessary software. Especially in the debugging phase of the module the software is continuously changed and updated. At the same time FPGAs are reprogrammed and the address table for the module changes. This procedure is relatively

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User Program

Reader Sequence (optional)

Reader VME64x configurator

Reader AddressTable

BusAdapter (PCI/VME)

HAL Hardware Access Library HardwareDevice

Device Driver

Hardware Module

Figure 10: Functional blocks of the Hardware Access Library. A dashed arrow means an optional information flow.[16]

time consuming since it involves repetitive changes of the source code with recompilation and debugging cycles.[16]

5.5 FEC

According to the official FEC software documentation, the FEC software needs only HAL and CAEN drivers for compiling and working properly [14]. Compiling errors were continuously telling something else. The frequently changing address of the documentation web page did not help us to compile the software. The only way to install the FEC software was the installFEC.sh script developed by the FEC software developer Frédéric Drouhin. The script downloads all the necessary programs—also those not men- tioned in the documentation—and compiles the FEC software.

The scriptinstallFEC.shdownloads HAL version 03-06. Luckily the FEC software 2005-11-30 CVS version is also compatible with HAL version 03-09. After the FEC software installation HAL was upgraded and FEC had to be recompiled.

In the test setup the only tool provided by the FEC software used wasProgramTest.

This tool gives all functionalities needed to access the FEC, CCU, rings (configuration)

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and devices (Tracker). In the test setup this executable is used to reset the FEC and CCU.

5.5.1 FEC software installation

The FEC software was installed by installFEC.sh script developed by Frédéric Drouhin. This script is available in CMS document server

http://cmsdoc.cern.ch/cms/cmt/online/doc/.

First the script installs the software needed by FEC. These software are XDAQ 3.21 and software packageshardware.tgzandoracle.tgz. The hardware package contains HAL version 03-06 and CAEN and SBS drivers. The script also downloads FED 9U software package and sets necessary environment variables. Finally the script downloads the latest CVS version of the FEC software and compiles it. Immediately after running the script the HAL was updated to the latest version 03-09 and FEC was recompiled.

The automatically downloaded FED software is not needed in our test setup as it is useless without the Front End Driver (FED) 9U card installed into the VME crate. The FED card’s task is to digitize the signals given by detectors. The FED software lacks documentation.

The installation script also installed a customized Oracle database package. This is not needed in our test setup.

5.6 RPC Trigger software

The RPC Trigger (RPCT) software package was developed at Warsaw University. It is used for reading the data from link boards.

The RPCT software package contains three tools: ttccommand.exe,vmeacc.exe andpulses_v2.exe. The vmeacc.exeis a simple program to do VME access by giving address and data, the ttccommand.exesends a trigger pulse from the TTCvi card and the pulse tool is only usable with a test pulse board described in 4.4. The pulse software utilizes the rate histogram module in the link board FPGA. This module is also called multichannel counter. The multichannel counters count the number of input signals simultaneously for every channel.

The RPCT software does not work if portmap service is not running. Portmap is a server

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that converts Remote Procedure Calling program numbers into DARPA protocol port

numbers. It is easy to check the status of services by command/sbin/service -status-all.

Portmap service can be enabled automatically at startup by writing a command

chkconfig portmap on as root. One has to remember that portmap is a potential security risk: check the firewall settings for preventing unwanted connections.

5.7 Linux JTAG Xilinx Programmer

Linux JTAG Xilinx Programmer is a software created by Rene van Leuken from Delft University of Technology in The Netherlands. The program is created to program Xilinx Virtex and Spartan FPGA chips. The license of the program is GPL. [17]

For the FPGA chip programming a Xilinx JTAG cable is needed. The cable is connected to the parallel port of the computer. Thus a user must have read and write permissions to the parallel port device. These permissions can be changed by command chmod 777 /dev/parport0as userroot.

In tests run in Lappeenranta University of Technology the binary of Linux JTAG Xilinx Programmer is never called directly. It is always run as script boot_cb which sends the FPGA code to the Control Board. In that case a user wants to run the program, the binary is calledxilinx-jtagand it needs two options, the binary code—for example cbic.bit—and the parallel port device file which is/dev/parport0.

5.8 System description file

The test setup has to contain a system description file. The task of the file is to describe the content of the VME crate and the link box. The RPCT software package tools will look for the installed devices and their addresses in the file.

The system description file also makes possible to use short address numbers for link boards. In the example below is a line which tells the link board (stdlb) number 4 address is 210. Thus it is easy to install VHDL code to this link board by simply referring it as link board number 4.

<?xml version="1.0" encoding="UTF-8"?>

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<!--<crate type="vme" id="100" desc="VME Crate">

<!-- <mezz type="2opto" pos="3" id="111" desc="opto 3"/>

<!-- <mezz type="2opto" pos="2" id="112" desc="opto 2"/>

</board>

</crate> -->

</crate>

<!--<link id="500" fromid="210" toid="111" toslot="0" desc="link 1"/>

</system>

5.9 Boost

Boost is a C++ source library. It is an open source project registered at SourceForge.net.

The library itself is useless without any software which needs it. In our test setup it is needed by the RPCT software package. [18]

6 Running tests

After booting the Linux computer and the VME crate and the link box, the user has to login to the computer as a test runner. All our tests are run by userajaja. After login, the following scripts needs to be run. These scripts are equal to those used in Warsaw university.

. bin/env.sh . bin/boot_cb . bin/reset_fec . bin/reset_ccu

The first script,env.shloads the environment variables. The script mainly adds XDAQ libraries toLD_LIBRARY_PATH.

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The scriptboot_cbloads the control board FPGA code developed by Wojciech Zabolotny from Warsaw University. The newest CB code is dated 2005-06-16. The script simply calls thexilinx-jtagand gives two parameters to it: the binary file to be loaded and the parallel port device. Below is an example of running the script.

[s293026] /home/ajaja/bin > . boot_cb Design Name: cbic.ncd

Device: 2s300eft256 Date: 2004/ 6/16 Time: 23:10:14

Bitstream Length: 1875648 bits Device ID: 90a20093

Manuf: 49, Part Size: 20, Family Code: 5, Revision: 9

Programming ... *******

Programmed 1875648 bits

The scriptsreset_fecandreset_ccuboth contain only one line and both resets are done by program ProgramTest.exe. Depending on the FEC card, the ProgramTest needs some mandatory options. In our test setup the options are -vmecaenpci and -fec 8. The first option is for CAEN controlled VME FEC and the second is needed when the FEC bus number is not equal to zero.

The FEC reset is made simply with ProgramTest option -reset. The FEC reseting should return address 0xc90 if the CCU ring is connected or address 0x490 if CCU ring is disconnected. If the returned address is different, the FEC must be reset again.

Also rebooting the crate can help. The CCU reseting is done by sending a special ASCII file with option-filecommand.

Here is an example of thereset_fecoutput:

[s293026] /home/ajaja/bin > ./reset_fec

VME FEC will be used with the file /usr/local/xdaq/TrackerOnline/2005/FecSof twareV3_0//config/FecAddressTable.dat

Make the configuration for - reset all PLX and FECs Press <Enter> to continue ...

--- Reset PLXs and FECs

--- A crate reset is done, not a board or a FEC reset

Value of the Status Register 0 of the FEC 8 ring 0: 0xc90 FIFO receive empty

FIFO return empty FIFO transmit empty Link initialise

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Example of thereset_ccuoutput:

[s293026] /home/ajaja/bin > ./reset_ccu VME FEC will be used with the file

/usr/local/xdaq/TrackerOnline/2005/FecSoftwareV3_0/config/FecAddressTable.dat Make the configuration for

- the file /home/ajaja/bin/memBusTest.txt Press <Enter> to continue ...

--- Read frame from the file /home/ajaja/bin/memBusTest.txt and send it onto the FEC ring

--- A crate reset is done, not a board or a FEC reset

Status register of the FEC = 0xc90

# Reset

writeFrame ( { 0x50 0x0 0x4 0x0 0x0 0x0 0x8080 } )

Trame direct ( { 0x50 0x0 0x4 0x0 0x0 0x0 0x8080 0x0 0x0 0x0 } ) Press enter to continue

Press enter to continue

The next step is opening the CCU server program by command./ccu_server. After textDONEappears on the screen, a CCU client program can be started in a new terminal window. Before starting the client, one has to run the environment in the new terminal.

The command for CCU client is./ccu_client. When the character >will appear on the screen, the following commands needs to be written in the client window:

scr mscb

px 4 rpc_lbstd_syncoder.bin

The first line is always the same, it loads the scriptmscb. This script loads filesmlbc andfcbpcto FPGA chips on CB. Also the script writes two numbers to CB and reads three registers. All three registers should contain a hex numberffefwhich the program prints into the window.

The second line is for programming the link board FPGA and it varies from system to system. The number in the second line tells the link board number. The number can be read from the crate front plane; the control board number is−1, the next slot is zero and so on. The string after the link board number is the binary file which will be sent to the link board. Currently the file used isrpc_lbstd_syncoder.binand it is developed by Krzysztof Pozniak from Warsaw University. The FPGA programming procedure must be done for all master and slave link boards in the crate. During the FPGA programming there will be lots of hexadecimal numbers in the CCU server window.

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An example of CCU client commands and output:

[s293026] /home/ajaja/bin > ./ccu_client

FEC 8 ring 0 CR0 = 0x0 SR0 = 0x3c80 SR1 = 0x8

> scr mscb ffef ffef ffef

> px 4 rpc_lbstd_syncoder.bin

The setup is ready for testing. Test can be performed with the programspulses.exe, pulses_v2.exeandsystest.exefrom RPCT software package. All the tests must be run in a new terminal window—the two open terminals are reserved for the CCU server and client.

6.1 Commands in a nutshell

Here all the commands needed for testing are listed.

cd bin . env.sh . boot_cb

. reset_fec (output should contain0xc90or0x490) . reset_ccu

./ccu_server (wait forDONE)

./ccu_client (wait for>)

scr mscb (wait for3×ffef) px 4 rpc_lbstd_syncoder.bin

./systest.exe ./pulses.exe ./pulses_v2.exe

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7 Link Board testing

The final link boards are designed by the Electronics Design Center of Lappeenranta University of Technology. The link boards will also be produced in Finland. For ensuring the production of working cards, a test card was designed. The task of the test card developed by Arja Korpela is to detect all possible errors in the link board production.

The test procedure is easy to make in a factory: the test card is connected to the link board and to the computer, the FPGA code is uploaded to the link board, and the test is run by pressing key ”t” from the computer keyboard. The computer screen and test board leds will tell the success of the test. The test flow is presented in figure 11.

L P C 2 1 0 4 X C 3 S 1 0 0 0 L i n k B o a r d

T e r m i n a l p r o g r a m

U s e r i n p u t

t e s t

t e s t r e a d y r e s u l t s

r e s u l t s

t e s t c o n n e c t i o n s

l e d s

Figure 11: The LB test card work flow. [7]

The link board test card has a Philips ARM based LPC2104 processor and a FPGA chip.

During the test all three FPGA chips (one in the test card and two in the link board) and the ARM processor need a special software. All test software for Philips ARM and Xilinx FPGAs were developed at Laboratory of Microelectronics at Lappeenranta University of Technology. The main developers were Ahti Karjalainen, Vesa Väisänen and Ville Vehmaa. The wire connection chart of the link board testing is in figure 12.

There are five tests performed by the test software. The tests cover the FEB connectors, GOL, CSC data connector and the front plane connector. Test success will be shown on the computer screen. An example of output is given below:

Lappeenranta University of Technology Department of Electrical Engineering

Press button ’t’ to start link board testing.

Waiting for test ready signal Press button ’s’ to skip...

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F P G A ( M ) X i l i n x S p a r t a n F G 4 5 6

5x

2 5 l e d s ( 1 2 )

5 0

2x

4 0

2x50

o p t i c a l i n p u t

R S 2 3 2

A : H i g h s p e e d d i f f e r e n t i a l l i n e r e c e i v e r 7 5 L V D S 3 8 6 B : H i g h s p e e d d i f f e r e n t i a l l i n e d r i v e r 7 5 L V D S 3 8 7 C : 1 . 5 t o 2 . 5 G B P S T r a n c e i v e r T L K 2 5 0 1 k ä y t t ö j ä n n i t t e e t j a m a a s i g n a a l i t

CA B 2x40

A

1 6

8

1 6 8 1 6

3 2

1 6

8

9 0

3 2 1 6

2 2 ( 1 6 ) 1 . 6 G B P S

64BBA ^{1 6}

3 2

BBA ^{1 6}

3 2

B

A8 4

P r o c e s s o r L P C 2 1 0 6

1 2

2 8

F P G A ( S ) U 2 X i l i n x S p a r t a n F G 4 5 6

5x

2 5 5 0

2x

4 0

2x50

o p t i c a l o u t p u t

G O L

B A 2x40

B

1 6

8

1 6

8

3 2

1 6

8

3 2 1 6

3 2 1 . 6 G B P S

64AAB ^{1 6}

3 2

AAB ^{1 6}

3 2

A

B8 4

F P G A ( S ) U 1 X i l i n x S p a r t a n F G 4 5 6

1 6 1 6

5 5

9 0

4 0 L V D S 9 0

4 8

L V D S 1 9 2

L V D S T E S T B O A R D

L I N K B O A R D

Figure 12: The test board connected to the link board. [19]

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***********************

FEB connector test FAILED GOL connection test FAILED CSC connector test FAILED

Front Plane connector test FAILED LB test pulse connection test FAILED

***********************

8 Conclusions

All the software used in the test setup has reached a stable status. These software packages were compiled succesfully and compatible with each other only recently. This tells about a long and difficult development of the software packages. The CMS experiment seems to be one step closer, as our link system test setup is working with the following software:

• Scientific Linux 3

• XDAQ 3.21 or newer

• CAEN driver version 2.3

• Hardware Access Library version 03-09

• FEC software CVS version, 2005-11-30 or later

• RPC Trigger software package, 2005-12-02 or later

• Linux JTAG programmer

• Boost C++ library version 1.33.1 or later

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References

[1] Ungaro, Donatella 2004. The Link-Board Control in the RPC Trigger System for the CMS experiment. Helsinki Institute Of Physics. 148 pages.

[2] Axer, Markus 2003. Development of a Test System for the Qual- ity Assurance of Silicon Microstrip Detectors for the Inner Track- ing System of the CMS Experiment. [web document] Available at:

http://www.physik.rwth-aachen.de/group/IIIphys/CMS/tracker/en/papers.html#theses.

Referred 2005-08-25.

[3] Brüning, Oliver 2005. Accelerators. [web document] Available at:

http://agenda.cern.ch/askArchive.php

?base=agenda&categ=a054021&id=a054021/transparencies.Referred 2005-08-25.

[4] The Tridas Project Technical Design Report, Volume 1: The Trigger Systems 2000. 630 pages. [web document] Available at:

http://doc.cern.ch//archive/electronic/other/generic/public/cer-002248791.pdf . Referred 2006-11-16.

[5] CMS Collaboration. 3D drawing of CMS, with re-

alistic colouring. [web document] Available at:

http://cmsdoc.cern.ch/cms/outreach/html/CMSdocuments/DetectorDrawings/DetectorDrawings.html

Referred 2005-09-14.

[6] Zabolotny, Wojciech. RPC Muon Trigger DCS System. Presented at CPT Week, CERN 2003-11-04 [web document], available at:

http://pccms9.igf.fuw.edu.pl/users/kudla/konferencje/cpt0311/wzab_cpt_0311.pdf . Referred 2005-11-07

[7] Väisänen, Vesa 2005. Muon Detector Link System Test Setup-Up. Lappeenranta University of Technology. 53 pages.

[8] Zabolotny, Wojciech. RPC Muon Trigger Link Sys-

tem. CMS Week. [web document], available at:

http://pccms9.igf.fuw.edu.pl/users/kudla/konferencje/week0403/ESRwzab.pdf. Referred 2005-12-07

[9] Welcome to Scientific Linux [web document], available at:

https://www.scientificlinux.org. Referred 2005-11-24

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[10] What is Scientific Linux CERN 4 (SLC). [web document] Available at:

http://linux.web.cern.ch/linux/scientific4/Referred 2005-09-28

[11] Data acquisition from Wikipedia, the free encyclopedia [web document], available at:http://en.wikipedia.org/wiki/Data_acquisitionReferred 2005-11-02

[12] Brigljevic, V. et al. Using XDAQ in Application Scenar- ios of the CMS Experiment. [web document], available at:

www.slac.stanford.edu/econf/C0303241/proc/papers/MOGT008.PDF Referred 2005-11- 02

[13] SourceForge.net - Project Info - XDAQ [web document], available at:

http://sourceforge.net/projects/xdaq/Referred 2005-11-02

[14] Drouhin, Frédéric. FecSoftwareV3_0. [web document] Available at:

http://x5oracle.cern.ch:8080/JSPWiki/Wiki.jsp?page=FecSoftwareV3_0 Referred 2005- 10-14

[15] Schwick, Christoph. HAL (Hardware Access Library) [web document], available at: http://cmsdoc.cern.ch/~cschwick/software/documentation/HAL/index.htmlRe- ferred 2005-10-21

[16] HAL Users Guide. [web document], available at:

http://cmsdoc.cern.ch/~cschwick/software/documentation/HAL/manual/HALUsersGuide.pdf

Referred 2005-11-02

[17] van Leuken, Rene. Xilinx JTAG programming software [web document], available at:http://cas.et.tudelft.nl/~rene/xilinx-jtag.cReferred 2005-10-17

[18] Boost C++ libraries [web document], available a: http://www.boost.org. Referred 2005-12-01

[19] Korpela, Arja 2005. Tuotannollisen testerin suunnittelu tiedonsiirtolinkkikortille.

Lappeenranta University of Technology. 57 pages. Referred 2006-01-10

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/***************************************************************************

Program for the Link Board tester.

Target device: Philips LPC2104 ARM

Waits for user input from terminal program via RS-232 and after receiving character ’t’ sends logic ’1’ to pin 11

so that the test board FPGA begins the testing. When the test results are ready the FPGA sends logic ’1’ to pin 10. After

that the results are read from the pins 8,9,22,23,24 and analyzed.

The report is sent to PC via RS-232 and the first six leds on the board are used to indicate if the tests were OK or FAIL.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software

Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA

Lappeenranta University of Technology Department of Electrical Engineering Vesa Väisänen & Ville Vehmaa 2005

**************************************************************************/

#include "lpc210x_gnuarm.h"

#include "config.h"

#include "uart.h"

#define BAUD 115200

/* DEFINITIONS */

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#define TESTPIN 11

#define TESTREADYPIN 10

#define SER1 24

#define SER2 23

#define SER3 22

#define SER4 9

#define SER5 8

#define LED1 12

#define LED2 25

#define LED3 26

#define LED4 13

#define LED5 15

#define LED6 16

#define LED7 17

#define LED8 18

#define LED9 19

#define LED10 6

#define LED11 5

#define LED12 4

volatile int res[5]; // Result chart, six results where 1=OK and 0=FAIL volatile int ch; // Index for the chart

void delay(void) {

int x,y;

for (x=0;x<4000;x++) for (y=0;y<2000;y++);

}

void systemInit(void) {

// --- enable and connect the PLL (Phase Locked Loop) --- // a. set multiplier and divider

SCB_PLLCFG = MSEL | (1<<PSEL1) | (0<<PSEL0);

// b. enable PLL

SCB_PLLCON = (1<<PLLE);

// c. feed sequence SCB_PLLFEED = PLL_FEED1;

SCB_PLLFEED = PLL_FEED2;

// d. wait for PLL lock (PLOCK bit is set if locked) while (!(SCB_PLLSTAT & (1<<PLOCK)));

// e. connect (and enable) PLL

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SCB_PLLCON = (1<<PLLE) | (1<<PLLC);

// f. feed sequence SCB_PLLFEED = PLL_FEED1;

SCB_PLLFEED = PLL_FEED2;

// --- setup and enable the MAM (Memory Accelerator Module) --- // a. start change by turning of the MAM (redundant)

MAM_MAMCR = 0;

// b. set MAM-Fetch cycle to 3 cclk as recommended for >40MHz MAM_MAMTIM = MAM_FETCH;

// c. enable MAM MAM_MAMCR = MAM_MODE;

// --- set VPB speed --- SCB_VPBDIV = VPBDIV_VAL;

// --- map INT-vector ---

#if defined(RAM_RUN)

SCB_MEMMAP = MEMMAP_USER_RAM_MODE;

#elif defined(ROM_RUN)

SCB_MEMMAP = MEMMAP_USER_FLASH_MODE;

#else

#error RUN_MODE not defined!

#endif }

/*

** LED Switching

**

** ledON(rs,1) switch on all leds valued 1

** ledON(rs,0) switch on all leds valued 0

** ledOFF(rs,1) switch off all leds valued 1

** ledOFF(rs,0) switch off all leds valued 0

*/

void ledON(int rs[5], int zeroone) {

if(rs[0]==zeroone) {

GPIO_IOCLR = (1<<LED1);

}

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}

} }

void ledOFF(int rs[5], int zeroone) {

GPIO_IOSET = (1<<LED1);

}

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} }

/* Initialize led pins as outputs and pull them high (off, as active low) */

void ledInit(void) {

GPIO_IODIR |= (1<<LED1);

}

/* Initialize pins between FPGA and LPC2104 */

void pinInit(void) {

GPIO_IODIR |= (1<<TESTPIN); // Test pin as output

GPIO_IODIR &= ~(1<<TESTREADYPIN); // Test ready as input GPIO_IODIR &= ~(1<<SER1); // Parallel data pins as inputs GPIO_IODIR &= ~(1<<SER2);

GPIO_IODIR &= ~(1<<SER3);

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}

int main(void) {

int countr=0;

int tr=0;

/* initializing the result chart */

for(ch=0;ch<6;ch++) {

res[ch]=’0’;

}

/* initializing leds (all off) */

ledInit();

/* leds on when power on */

/* initializing pins between FPGA and LPC2104 */

pinInit();

GPIO_IOCLR = (1<<TESTPIN); // Set test pin low systemInit();

uart0Init(UART_BAUD(BAUD), UART_8N1, UART_FIFO_8); // setup the UART while(1)

{

GPIO_IOCLR = (1<<LED12); // Power on LEDs GPIO_IOCLR = (1<<LED11);

delay();

uart0Puts("\r\nLappeenranta University of Technology\r\n");

uart0Puts("Department of Electrical Engineering\r\n");

uart0Puts("\r\nPress button ’t’ to start link board testing.\r\n");

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/* wait until the button ’t’ is pressed */

while((ch = uart0Getch()) != ’t’) { }

/* send the TEST signal to FPGA to start testing */

GPIO_IOSET = (1<<TESTPIN);

tr=0;

uart0Puts("\r\nWaiting for test ready signal\r\n");

uart0Puts("Press button ’s’ to skip waiting...\r\n");

/* wait until TESTREADY signal gets value 1 */

/* This can be skipped by pressing button ’s’ from the terminal */

while(tr==0) {

if(GPIO_IOPIN & (1<<TESTREADYPIN)) tr=1;

else { tr=0;

if((ch = uart0Getch()) == ’s’) tr=1;

} }

/* reading and printing the results */

if(GPIO_IOPIN & (1<<SER1)) {

res[0]=’1’;

uart0Puts("\r\n***********************\r\n");

uart0Puts("FEB connectors test OK\r\n");

} else {

uart0Puts("\r\n***********************\r\n");

uart0Puts("FEB connector test FAILED\r\n");

}

if(GPIO_IOPIN & (1<<SER2)) {

res[1]=’1’;

uart0Puts("GOL connection test OK\r\n");

} else {

Muon Detector Link System Test Setup Software