Abstract— Printed Electronics Technologies add new fabrication concepts to the classical set of microelectronic processes. Among them, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to use such property: (1) wiring new metallic layers on top of the circuit to build PLA-like circuits, (2) program OTP ROM like memories or (3) build Inkjet-Configurable Gate Arrays (IGA). The capability of building an individual circuit with technological steps simpler than photolithographic ones is opening a concept similar to the successful Field Programmable Gate Array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the Drop-on-Demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by 2 different DoD technologies: Inkjet and Superfine jet, and have been compared to mask-based photolithography technology with promising results.
Index Terms— Interconnection, Digital circuits, Organic and Printed electronics, Drop-on-demand, Digital Printing, Inkjet Configurable Gate Array, Inkjet, Superfine jet, Photolithography.
The paper has been submitted for review on 05/12/2016. This work was partially done with the support of the Spanish government funded project MEF3_IRX (TEC2014-59679) and through work funded by NeuDrive Limited. M. Mäntysalo is supported by Academy of Finland grant no. 288945.
M. Mashayekhi is with CEPHIS (Center for Hardware – Software prototypes and Solutions) at UAB University (e-mail:
mohammad.mashayekhi@uab.cat)
L. Winchester is with Centre for Process Innovation (CPI) at UK.
(Lee.Winchester@uk-cpi.com)
M.-M.Laurila and M. Mäntysalo are with Department of Electronics, Tampere University of technology, Finland (mika-matti.laurila@tut.fi, matti.mantysalo@tut.fi)
S. Ogier is with NeuDrive Limited, a UK based OSC Materials Company.
(simon.ogier@neudrive.com)
L. Terés is head of Integrated Circuits & Systems (ICAS) group at the National Centre for Microelectronics, Barcelona Microelectronics Institute, IMB-CNM (CSIC) (lluis.teres@imb-cnm.csic.es)
J. Carrabina is heading the research group Embedded Computation in HW/SW Platforms and Systems Laboratory and CEPHIS (CSIC-Consejo Superior de Investigaciones Cientificas- Associated Unit) at UAB Universidad Autonoma de Barcelona-Spain (jordi.carrabina@uab.cat).
I. INTRODUCTION
ETEROGENEOUS integration of multiple functional platforms, which might differ in feature size and materials, into a single chip is the key driver for a wide variety of application fields. As the device sizes shrink and the functionality of heterogeneous integration gains importance, high throughput pick-and-place techniques, capable of handling many components, will become critical.
Thus, the need for economically viable technologies, which provide this integration on host substrate with required accuracy and yields, is inevitable.
H
Printed and organic electronics, as a comprehensive More- than-More technology, have attracted much attention in recent years due to their compatibility with flexible substrates, low temperature additive fabrication processes, large-area processing and low-cost. The key benefits of the technology are flexibility, low environmental impact and extremely light- weight at potentially low-cost. This has highly stimulated the research and development in organic materials, devices and circuits.
Organic electronics are emerging as complementary to silicon electronics for some commercial applications such as pixel driver circuitry for active-matrix backplanes in displays [1]-[3], RFID tags [4]-[6], smart sensor systems [7], flexible batteries [8], organic memories [9], and even flexible processors [10]. Electronics and components have a set of different driving forces in Internet of Things (IoT) era for printed electronics. This requires seamless integration of relatively simple electronics, both for digital and analog circuits. Significant further cross disciplinary efforts will therefore be required by chemists, printing technology specialists, and electronic circuit designers.
Currently, most organic electronic circuits are designed by specifying the layout of each individual transistor and their interconnections; using a full-custom design methodology.
Full-custom design is time consuming for complex circuits, and it has the potential for low yield at circuit level, since the failure of one transistor often will have a serious impact on the entire circuit functionality. Additionally several mask sets are required in order to transfer the circuit designs onto the wafer, and the mask cost is not shared between different applications.
In contrast, array-based semi-custom design methodologies alleviate the often prohibitive time and expense of design and fabrication, by separating the master slice manufacturing process from Back End Of Line (BEOL) metallization step.
Devices that are made of layers stack (e.g. transistors and Mohammad Mashayekhi, Lee Winchester, Mika-Matti Laurila, Matti Mäntysalo, Simon Ogier, Lluís
Terés, Jordi Carrabina
Chip-by-Chip Configurable Interconnection
using Digital Printing Techniques
gates) can take the advantages of complex mask-based processes, while low complex interconnection techniques can be used in BEOL metallization step. We have presented Inkjet- Configurable Gate Array (IGA) as a design manufacturing methodology for individual personalization of organic electronic circuits, bringing together the concepts of silicon gate array and field-configurability, through the best use of digital printing technologies [11].
Similarly, in the Internet of Things (IoT) era, devices need both identification and personalization, which can be provided at circuit level by low-cost digital Drop-on-Demand (DoD) and mask-less printing technologies. These technologies are often less complex comparing with mask-based processes such as photolithography-metallization, fuses, dual-gate devices and etc. It also enables metallization of configurable circuit in-the- field (at home) without the need to returning or disassembling the chip to its manufacturer.
One target for development of organic circuits is to optimize the fabrication processes to achieve a sufficiently high integration density at a suitable operating frequency for applications. At the same time yield and material waste reduction must also be improved to make the technology commercially viable.
In order to increase the circuit density, several circuit design methodologies and technological approaches have been presented. FPGAs or Sea-of-Gates (SoG) methodology, use regular structures together with complex wiring by increasing number of metal wiring layers. Each one of these approaches possesses inherent challenges and limitations. Shrinking down the metal line width and space reduces conductance of connections and thus increases wire delay. Adding wiring layers is a straightforward means of providing greater function density per circuit. However, added layers invariably translate to added cost. It is therefore imperative to make the most efficient use of real estate used for wiring in order to keep the number of wiring layers to a minimum.
Thus, the challenge is to reach the highest possible DoD wiring density according to any given personalization requested by the circuit functionality (including identification, implementing specific functions as coding, calibration and etc.). This will overcome the difference between the resolution of the photolithographic master circuit and the personalization wiring technology.
In the next section we present the new drop-on-demand via concept. Section III details the interconnection structure and its corresponding designed test vehicles as well as the process layers. In section IV, both digital printing and photolithographic techniques are tested for wiring the test vehicles. Section V shows and evaluated the results obtained from the printed connections, and section VI presents some circuits implemented on inkjet-configurable gate arrays (IGA) using the proposed structure for wire cells.
II. DOD VIAS
The novel approach described in this paper permits functionality, efficiency and density improvement in printed circuits (although it is also applicable to integrated circuit). It
is funded in the development of a reliable interconnection based on building a metallic DoD bank. These wiring structures are selective interconnecting devices and/or terminals, and can be viewed as a metallization step on top of unconnected OTFT devices, cells or arrays to provide any given functionality [12].
The main advantage of single DoD processing step, as an alternative to lithography, is that it offers a rapid circuit personalization function that can be done differently for every individual circuit, saving on mask production costs.
Low-resistivity and reliable wiring of the well proven pre- defined logic cells can eventually lead to robust complex digital circuits. Furthermore, digital printing allows that different circuits can be personalized according to specific properties, such as circuit identification number (i.e. Ethernet MAC address) or fault tolerant techniques (i.e. wiring only known good transistors [13],[14]), changing functionalities (i.e. for changing polynomials for code generation).
Some works have also introduced the use of inkjet printing for building circuits. In 2013, Koichi Ishida et al. presented the User Customizable Logic Paper (UCLP) with IJ printed interconnects by using 200 µm via whole in diameter with 300 µm misalignment error of off-the-shelf family-use printer [15].
Later in 2014, Antony Sou et al. proposed programmable Logic Circuits (PAL) for functional integrated smart plastic systems [16], in which the final metallization step is realized by inkjet printing of conductive interconnects with minimum design rule for wire width and separation of 250 µm. In 2013, M. Peter et al. proposed an interconnection technology by filling laser drilled through vias, in which the minimum via dimension of 100µm was achieved and it also requires additional laser processing for drilling vias [17]. All of those promising interconnection techniques are subjected to the low resolution of the digital printing techniques in metallization step, which reduces the circuit density of the high-resolution patterned circuit.
Other works have shown the use of inkjet printing for BEOL metallization of prefabricated silicon or flexible chips with higher printing resolution and integration density. In 1999, Doland J. Hayas et al. presented the MicroJet printing of solder and polymers for chip scale packaging and multi-chip modules [18]. In 2011, Falat et al showed nano-silver inkjet printed interconnections through the Microvias [19], and later in 2013, Quack et al demonstrated the use of inkjet printing for Through Silicon Vias (TSV) and thermo-compression bonding for heterogeneous MEMS integration applications [20].
However, using these micro-jet technologies for metallization of organic and flexible configurable circuits have some limitations. Some of these techniques use Deep Reactive Ion Etching (DRIE) or laser drilling for formation of deep vertical via structure. Besides, inkjet based printing processes happens at high operating temperatures up to 300°C. These via formation and high temperature jetting techniques can damage the pre-fabricated circuit specially the organic semiconductor materials.
Previously, we presented interconnection structures compatible with digital printing technologies such Superfine
Jet or Aerosol Jet with minimum width and spacing of around 20 µm but those could not achieve 100% yield and reliability [21]. Digital inkjet printing of long conductive tracks may result in unreliable connections or short circuits between terminals, due to digital printing variability for physical effects like line scalloping or bulging when high resolution printing is required.
In order to overcome this issue, the spacing between wiring connections need to be increased, which decreases wiring integration density for a given number of devices.
Additionally, in order to print a fine line by using digital printing techniques, such as IJ or SIJ, previously printed materials must withstand the harsh process conditions that include several heating cycles in relatively high temperatures for organic materials.
In this work, we present a novel DoD interconnection methodology, which does not require any DRIE or laser drilling process for via formation, and it also can be metallized by cost-effective non-contact digital printing techniques such as inkjet. Furthermore, it increases the compatibility with conventional inkjet technique and overcome the issues with printing of long fine lines, hence, improving the integration density and reducing the undesired line scalloping or bulging.
III. CONNECTIONSTRUCTURE
The main idea to overcome the above-mentioned issues is to realize the selective interconnects by deposition of conductive dots/drops instead of printing conductive tracks.
This method partially eliminates or alleviates some of the limitations of previous implementations in which the interconnections were realized by printing short or in some cases long fine tracks [21].
The proposed connection structure is composed of two different elements: (1) the pre-defined high resolution photolithographic cross of metallic layers with a “bank”, and (2) the final customization inkjet drop. The final layout of the proposed structure, depicted in Fig. 1 (a) is oriented to obtain maximum wiring yield taking into account the fluidic properties of the jetted metallic drop. Cross section view of the structure in Fig. 1 (b) allows identifying the different layers involved in it:
• A first conductive track at the bottom
• An insulating layer with its via
• A inner area of the second conductive track covering the via and connecting with the first conductive layer
• An outside ring on the same second conductive layer that does not contact the inner area of the same layer.
• A further optional metallic DoD layer that, when present, will implement a short circuit between the inner area and outer ring and thus between first and second conductive tracks.
The combination of the first metal square, via opening, the inner square and outer ring of second metal is called bank, which is the desired location of final drop for providing the connection. In order to test the functionality of the proposed method and its applicability in circuit metallization, we designed some test vehicles similar to the wire cells in IGA.
Fig. 1. (a) Three dimensional representation of the layers stack composed of mask-based layers (metal and passivation) and metallic drops, (b) Cross
sectional view of the connection bank wired by MET3.
The fabrication process consists of photolithography of Au for two metal layers (MET1, MET2) upon glass substrate, and two photopolymer passivation layers (SU8) spin coated and patterned by photolithography with via opening of 10 um2 and 16 um2 on top of the MET1 squares. The proposed test vehicle is shown in Fig. 2. A micro-image of the unwired test vehicle manufactured at NeuDrive-CPI is shown in Fig. 2(d).
In order to improve the density of structure (less separation of MET1 horizontal wires), banks are placed in a Zig-Zag fashion. Connection between bottom pads
B
¿
¿¿
) and top pads
T (¿¿ i)
¿
, are implemented by printing a final drop of MET3 to short circuit the inner and outer shapes of the MET2 on the banks.
Fig. 2. Schematic of the test vehicles (a) Unconnected (b) Connected (c) Equivalent connection (d) Micrograph of the manufactured at Neudrive-CPI
We tested different metallization technologies and for that we used different design rules such as width and separations of
manufactured lines and via. Matrixes of test vehicles were designed using the freeware Glade IC layout editor [22] and a parameterizable cell (PCell) approach [23]. Fig. 3 shows a zoomed-in section of the metallized test vehicle with its design parameters. For bank width, the minimum possible value Wmin
is limited by the photolithography design rules. The minimum width of via openings for passivation layers are 10um and 16um and the width of inner MET2 square should respect the minimum overlap of MET2 layer with passivation. Thus, the width of inner MET2 square is set to Winner-MET2=22µm.
Besides, in order not to cause any unexpected short circuit between this square and the outer MET2 ring, the minimum MET2 separation (SMET2=5µm) should be respected, and eventually the outer ring needs to have the minimum MET2 width (WMET2=9µm). Taking all these rules into account the minimum bank width can be calculated as:
Wmin=Winner-MET2+2.SMET2+2.WMET2 = 22 + 10 + 18 = 50µm Thus, the designed range of bank width in the test vehicle array was: (W=50, 60, 70µm). Regarding the minimum separation, the range is (S=30, 40, 50µm), and the aim is to maximize the circuit density as much as possible.
Fig. 3. The design parameters of the drop-configurable wiring test vehicle
Additionally, a second test vehicle called “via chain” has been designed in order to check the repeatability of the connection banks. In this test vehicle, the width and space of the connection banks are kept constant (W=70µm, S=50µm), and a variable number of via banks (2, 4, 8, 16, 32) have been placed between two pads. The aim is to check the resistance between two pads after wiring the banks by filling the vias, in order to calculate the resistance per via accurately in this structure with the variability given by the DoD printing process.
The layout of unwired and wired test vehicles as well as its corresponding unwired manufactured structure including 8 vias between two pads are shown in Fig. 4 (a, b, c) respectively.
Fig. 4. Via chain test vehicles layout (a) Unconnected (b) Connected (c) Image of final fabricated via chain structure.
IV. METALLIZATIONTECHNIQUES
Both test vehicles were wired by using three different technologies. Firstly, inkjet (IJ) and Super-fine inkjet (SIJ) direct-write printing technologies were used, where the functional materials are controllably deposited onto samples.
The desired printing patterns are defined by EDA tools allowing rapid prototyping of several geometries without using photolithography. Material loss is minimal due to additive manufacturing by means of digital printing and no functional materials have to be removed as in mask-based processes.
Using additive digital printing gives further flexibility to the interconnection process by enabling individual chip-by-chip personalization and design changes at the last stage of the production chain.
In parallel, some test arrays were wired by using gold metal layer following the same photolithography process used for previous layers. This was expected to lead to the highest performance (i.e. lowest contact resistance), with good reliability and yield and hence was used for comparison with the connections produced by IJ and SIJ techniques.
A. Inkjet Printing (IJ)
Conventional inkjet process is seen as an attractive digital printing technique in fabricating organic devices and circuits.
Recently, lithography-free all-inkjet-printed flexible electronics were fabricated on a polymer substrate by laser sintering techniques [23]-[25]. IJP resolution is limited to 20- 50 micrometers due to the nature of the materials to be printed and also to the statistical variability provided by fluid-based piezoelectric deposition technologies, though physical effects such as the flight direction of droplets and variable wetting on substrates [26]-[29].
This variability can cause accidental electrical shorts or open circuits when printed onto the photolithographic patterned interconnection structures. Furthermore, when the desired patterns, especially fine lines, are printed onto the stack of layers with different features, the resolution and shape of the final printed line can change unpredictably, and a failure of one connection might cause the entire circuit to fail.
In this work, IJ printing is used with some ease due to the fact that the new via structure requires only discrete drops to be deposited. This significantly reduces the risk of printed line instabilities such as bulges or scallops as described earlier.
Wire test vehicles and via chain test vehicles shown in Figures 2 and 4 were wired by the IJ printing technique.
Dimatix DMP2831 printer was used to jet a conductive silver ink (Silverjet DGP-40LT-15C) with ink size distribution of 59±2 nm, through a 10 pL nozzle print head. The distance between the print head and the substrate was 300 µm. The substrate was heated to 60°C during printing and following printing the ink was cured at 115°C for 60 minutes.
Each printed connection consisted of a single pixel 10 pL droplet therefore any misdirected nozzle would result in a circuit failure. This was mitigated by inserting a leader pattern into the design. The leader pattern allowed the jetting to stabilize before the design was printed. This consisted of a series of 1 pixel drops located in an unobtrusive section of the
substrate.
Images of the printed features onto wire test structures and via chain test vehicles are shown in Figures 5 (a) and (c).
Figure 5 (b) also shows the zoomed in image of adjacent IJ wired and unwired via structures. The ink adapts to the shape of the square via and covers both (top and bottom) metal layers of the bank structure, including the gap between the center and the square ring in the bank of the top metal layer.
Fig. 5. IJ wired (a) wire test structure, (b) zoomed-in via, and (c) via chain
B. Superfine Inkjet Printing (SIJ)
SIJ technology was developed by Japan´s National Institute of Advance Industrial Science and Technology (AIST) and further commercialized by SIJ Technology Inc. The equipment draws its heritage from electrospraying technology used for atomization of liquid; it is a type of electrohydrodynamic (EHD) printing process, which utilizes oscillating electric field to generate the necessary pressure for droplet ejection. This enables the generation of sub-femtoliter droplets and micron- scale resolution when the substrate wetting conditions are suitable [30]-[32]. The large surface area to volume ratio of the in-flight droplets and the resultant fast evaporation rate of solvent can be also utilized in fast printing of three dimensional structures such as pillars and bumps [33]. The bumping approach is especially interesting here since it would allow for fast buildup of thick interconnects in MET3.
ULVAC Au-ink was chosen as the best candidate for the printing tests due to its high boiling point solvent (Cyclododecene, Tboil=232℃¿ which leads to slow solvent evaporation rate at the nozzle tip and reduced possibility of clogged nozzle due to drying up of the ink. The material and processing parameters of the ink are given in Table 1.
Table 1
ULVAC Au-ink parameters [34]
Parameter Value
Solid content 50 wt%
Nanoparticle size 10 nm
Sintering condition 250ᵒC for 60 min
Resistivity 8
μ Ω. cm
Solvent Cyclododecene
Before carrying out the printing trials the substrate surface was cleaned and activated using ten minutes of oxygen plasma cleaning with O2 flow of 2 sccm, pressure of 100 mTorr and RF power of 100 W.
Printing of the MET3 interconnects was accomplished by using a bumping mode whereby each bank is filled with multiple ink layers consisting of numerous sub-picoliter sized droplets. The number of layers, the number and volume of the droplets in each layer and the idle time between the subsequent layers determine the volume and spreading of the bump. The latter affects especially the spreading of the ink since it determines how much of the solvent will evaporate between printing of the layers. If the spreading is not enough, the MET2 ring might not wet properly leading to open circuit whereas too large spreading might cause short circuits between subsequent vias. In this case the optimal results were achieved using the print parameters given in Table 2.
Bipolar jetting voltage ( VBias=0V ) was chosen to prevent possible charge accumulation on the surface, which might cause print artifacts such as droplet deflection [35].
Because of this, the droplet ejection frequency is twice the voltage frequency i.e. 140 Hz instead of 70 Hz; with 0.4 second holding time the resulting droplet number per layer will be 56. It must be noted here, that the VMax had to be decreased during the printing, as there was a tendency for the bumps to spread more as the printing proceeded.
Table 2
Print parameters for SIJ bumping
Parameter Value
Waveform Sine Wave
Vmax , Vbias 450 to 460 V, 0 V
Nozzle-to-substrate distance 100 µm
Voltage frequency 70 KHz
Holding time per layer 0.4 sec
Idle time between layers 1.2 sec
Number of layers per bump 40
Figure 6 (a) and (c) show an example of wire test and via chain structures filled with SIJ technology; (b) shows a zoomed in image of adjacent filled and unfilled vias.
Fig. 6. SIJ wired (a) wire test structure, (b) zoomed-in via, and (c) via chain
It can be seen that there is ample coverage between the MET2 ring and the center of the via, but also that the spreading could be further increased to get full coverage.
C. Photolithography
Photolithography is a high-throughput, high-resolution patterning processes in which geometric patterns on a mask are transferred into layers on the substrate. The process involves several steps such as cleaning, photoresist coating, baking, mask alignment/exposure, and patter developing. The technique is comparatively costly vs printing but it has been shown to be a very reliable technology for electronics.
A mask for (MET3) circuit wiring the designed test vehicles was designed, and transferred into the test structures in this layer. As presented in Figure 7, very fine and accurate connections have been observed.
Fig. 7. Photolithographic wired (a) wire test structure, (b) zoomed-in via, and (c) via chain
V. RESULTSANDEVALUATION
After optical characterization of 2 arrays of 9 test vehicles (18 test vehicles in total) with W=50, 60, 70 µm and S=30, 40, 50 µm, statistical results show that, the printed drops are well placed and cover the entire bank area without much extension or undesired short circuit for all cases, except S=30µm. When the minimum designed value for bank separation is S=30µm there are 2 and 3 failures for IJ-wired, and SIJ-wired test vehicles, respectively. These failures are due to small separation of banks, which cause undesired connection between the printed drops (shown in Fig. 8) and are considered as hard faults. Therefore, S=40µm is safe and can be considered as the minimum spacing between banks with 100%
yield and reliability.
Fig. 8. Occurrence of hard faults when wiring the test vehicles for S=30µm
According to the geometrical design rules of the photolithography technology, W=50µm is the minimum possible value for pre-defined bank structures. Results show that the minimum bank width is determined by this value, since all of the wires structures are well-covered.
It should also be mentioned that initially, some failures were detected caused by misalignment error, and it affected the entire array of test vehicle regardless of the bank width and separation. This error was caused by faulty nozzle and drop offset. In order to overcome this issue, the print head was replaced and the drop offset was recalculated for subsequent samples and substrates. Afterwards, 100% yield was obtained under good alignment conditions for wiring 18 new test vehicles.
In order to extract the contact resistance (RC) of filled banks for each metallization technology, the pad-to-pad resistance (RT) of four arrays of metalized via chain test vehicles were measured. Each array includes series of 2, 4, 8, 16, and 32 banks. The measured results show that the soft fault, caused by process variation, is not as much as line-configurable structures that were proposed in [21]. The reason is that the final printing layer in this methodology is not long wires, where the resistance would change dramatically depending on the width, length and thickness of the printed lines. The measured RT is separated into two resistive components between two pads:
a) Resistance of the MET1 and MET2 wires connecting to the pads ( RM¿
b) Contact resistance of the wired banks, multiplied by number of banks in series ( N . Rc¿
R
T= R
M+ N . R
C(1)
where N is the number of banks in the serial chain, and
R
M can be estimated by the classical expression (2) for the resistance of a rectangular three-dimensional conductor.R
M= R
sL W
(2)
Where “ Rs, L, W” are the sheet resistance, length and width for MET1 and MET2 wires. According to technology information, sheet resistance of MET1 and MET5 layers (with 50nm thickness) are 0.50 and 1 ohm/sq respectively. The width of all patterned lines is 10µm (minimum design rule
value). Expressions (1) and (2) were used to calculate the contact resistance of one single via metallized by two digital printing techniques (IJ and SIJ), as well as mask-based photolithography patterns.
Four arrays of via chain test vehicles were wired by each metallization technique. Figure 9 shows the average measured pad-to-pad resistance
R (¿¿ T )
¿
, metal line connection resistance (
R
M¿
, contact resistance of the series of wired viasN . R (¿¿ C)
¿
and contact resistance per single wired via
R (¿¿ C )
¿
.
Table 6 shows the summary of the average contact resistance per wired via for three metallization technologies. It demonstrates the feasibility of digital printing techniques (either high- or low-resolution) with the proposed drop- configurable wiring methodology. The calculated average contact resistance per bank for IJ and SIJ is pretty similar to PH one. These values are suitable for the implementation of digital circuits using high mobility OTFTs (typically these transistors have equivalent on-resistances of hundreds of kΩ).
Fig. 9. Resistance measurements and calculations for wired via banks
TABLE 6
AVERAGECONTACTRESISTANCEPERWIREDVIA
RCIJ RCSIJ RCPH
Average 19.2
(Ω)
12.6
(Ω)
11.2
(Ω)VI. CIRCUIT IMPLEMENTATION
In the proposed Inkjet-Configurable Gate Arrays (IGA) [11]
the first manufacturing step, which is the fabrication of the IGA bulk or master foils/chips through mask-based
photolithographic technology, is similar to conventional gate array industry. But, the second step (metallization) in silicon gate arrays, which requires generation of new mask(s) for individual circuit personalization, can be replaced by a single process of mask-less digital printing technique.
The main advantage of this approach is increasing
functional capabilities by using digital printing to customize every individual fabricated master slice (master foil) to its specific functionality. The use of additive mask-less printing techniques enables quick and accurate placement of wires and interconnects at lower cost, thus avoiding the need for EEPROM devices or a new mask for functionality
personalization. The basic structure of the IGA is illustrated in Fig. 10.
Fig. 10. Abstract view of the IGA structure
Inside the designed IGAs, the interconnection structure proposed in this paper has been used as the wiring cells.
Several IGA structures have been fabricated by through a 4µm channel length photolithographic process at CPI using FlexOS organic material developed by NeuDrive. Zero-VGS load inverters were IJ-wired onto the IGA, and the results are shown in [11, 36]. In this paper, we have IJ-wired a ring oscillator, as one of the most important and indicative circuits, which can give a comprehensive description of the printing technology and its adapted circuit design technique. Fig. 11 shows the schematic of the 5-stage ring oscillator with an output buffer.
Fig. 11. Schematic of a 5-stage ring oscillator with an output buffer
In order to clearly show the IJ printed drop, a portion of implemented ring oscillator is shown in Figure 12. Inkjet technique has been used only for wiring the pre-fabricated transistors and wire cells.
Fig. 12 Micrograph of a portion of the IJ-wired 5-stage ring oscillator [44]
20 ring oscillators were wired on different sections of 5 different IGA foils (10 IJ-wired, 10 Photolithography-wired).
All of the ring oscillators were tested by using the same pico- probe. It was found necessary to increase the supply voltage to 30 V to initiate stable oscillation with 40 V being typical. Fig.
13 (a) is a histogram, showing the number of wired ring oscillators with output frequency in the 10KHz band, and (b) is the output frequency versus p-p swing of the ring oscillator for 20 wired samples.
Fig. 14. shows the maximum frequency obtained by IJ- wired ring oscillators, which is 74KHz with 5.4 V output swing. The displayed output signal should be scaled by 1.8X to account for the probe impedance mismatch with the oscilloscope.
Fig. 13. IJ- and PH-wired ring oscillators inside photolithography IGAs (a) Histogram (b) Frequency vs. p-p output swing
Fig. 14. Output voltage of IJ-wired ring oscillator
The previously IJ-wired inverters in IGA have shown the high-to-low and low-to-high propagation delays equal to (TPHL=1.5µs and TPLH=0.7µs), therefore, the equivalent propagation delay of the IJ-wired inverters can be calculated from equation (3).
T
P= 0.5T
PHL+ 0.5T
PLH(3)
Therefore, TP is equal to:
T
P= 0.5( 1.5 )+ 0.5(0.7)
= 1.1 µsAccording to the stage delay of inverters, the expected oscillation frequency of the ring oscillators can be estimated by using the Equation 4, where N is the number of stages.
F=(2 N T
P)
-1(4)
Therefore, F is equal to:
F=(2∗5∗1.1 µs)
-1 = 91 KHzThe measured results show that the maximum oscillation frequencies (Fmeasured=74KHz) is close to the calculated value (Fcalculated=91KHz), and the small difference can be due to the fact that parasitic capacitance of the wiring cells in IGAs affect the ring oscillators more than single inverters. The average measured frequency of IJ-wired ring oscillators is (Faverage- IJ=54KHz), and for the PH-wired ones is (Faverage-PH=59KHz).
This shows a very good matching between two different metallization techniques, and makes inkjet the best candidate for IGA metallization.
VII. CONCLUSION
In this paper, we presented a method of implementing wiring connections using drop-on-demand (DoD) printing technologies. These connections allow new circuit functionalities related to individual chip-to-chip personalization of circuits that can be used for inkjet- configurable gate arrays (IGA), OTP ROM-like memories, PAL computing structures, etc.
The proposed connection structure is composed of a photolithographic bank, partially connected via and conductive ink drop that can be deposited by digital printing techniques such as inkjet or superfine jet.
Feasibility of digital printing techniques with different resolutions with the proposed structure has been demonstrated.
Test vehicles were designed and fabricated using photolithography that was subsequently wired by using a low resolution (IJ), and high resolution (SIJ) printing technologies.
Both IJ, and SIJ offer promising results, comparable with the corresponding photolithographic ones.
For the designed configurable via banks, the average contact resistance per wired via has been measured and calculated. SIJ
wired connections have a resistance equal to 12.6 ohm per via, which is only 1.4 ohm higher than photolithographic ones, while IJ printed connections are more resistive and show an average of 19.2 ohm per via resistance. Those measured values are still far less than the transistors on-resistance in organic electronics.
Comparing to line-configurable wire style [21], the results show that the resistance, yield, variability, and scalability of drop-configurable style have been largely improved and optimized. Besides, the compatibility of the proposed structure with inkjet printing, as the most cost-effective available digital printing technique, has made it the best candidate for wire channels in the IGAs. As a proof of concept, ring oscillator circuit has been implemented onto the IGA structures by using IJ printer.
ACKNOWLEDGMENT
The authors wish to thank Centre for Process Innovation and Technical University of Tampere for collaboration in the development of test structures and metallization. This work was partially done with the support of the Spanish government funded project TEC2014-59679 and through work funded by NeuDrive Limited. M. Mäntysalo is supported by Academy of Finland grant no. 288945.
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AUTHORS
Mohammad Mashayekhi received his M.Sc. & Ph.D. in electronic engineering from the Universitat Politécnica de Catalunya (UPC) and Universitat Autonoma de Barcelona (UAB), Spain in 2012 and 2016 respectively. He has participated in several national and European projects, and technology transfer contracts. Mohammad has an extensive experience in flexible, printed, and hybrid electronic products lifecycle from design and development to commercialization, with a knowledge of additive and subtractive processes, design automation, and EDA/CAD tools.
Lee Winchester received his MSc in Nanotechnology and Microsystems from Teesside University in 2010. He is currently working as a Printing Process Scientist at The Centre for Process Innovation (CPI) in Co. Durham UK. His research interests relate to the development of functional devices using aerosol jet deposition techniques.
Mika-Matti Laurila received his M.Sc.
in electrical engineering from Tampere University of Technology in 2015. He is currently working towards his Ph.D. at the Printable Electronics Research Group at
TUT. His research interests are related to the applications of inkjet technology in electronics packaging
Matti Mäntysalo received his M.Sc. and D.Sc. (Tech) degrees in electrical engineering Tampere University of Technology, Tampere, Finland in 2004 and 2008, respectively. He has been with the Printable Electronics Research Group, TUT, since 2008, where he is an Associate Professor with Electronics Materials and Manufacturing and an Academy Research Fellow. He has authored or co-authored more than 100 international journal and conference articles.
Simon Ogier graduated in Physics with Electronics and Instrumentation from Leeds University in 1996 and completed a PhD researching Molecular ion channels as novel biosensors in 2000. Since that time he has worked in the field of organic electronics, developing high performance organic semiconductors for transistor applications within companies such as Avecia (UK), Merck (UK), CPI (UK) and recently with NeuDrive Limited (Manchester, UK).
Lluís Terés was born in Aragón, Spain. He received the Engineering and Ph.D.
degrees in computer sciences from the Autonoma University of Barcelona (UAB), Barcelona, Spain, in 1981 and 1986, respectively. He has been with the National Centre for Microelectronics, Spanish National Research Council, Barcelona Institute, Barcelona, since 1985, where he is the Head of Integrated Circuits and Systems Group. He is also part-time Assistant Professor at UAB.
Jordi Carrabina received M.S. (1988) and Ph.D. (1991) degrees in Microelectronics (CS Program) from the University Autonoma of Barcelona (UAB), Spain. He joined the National Center for Microelectronics (Spanish National Research Council), Barcelona, in 1986.
Since 1990, he has been an Associate Professor with the Microelectronics Department, UAB, and lead CEPHIS (2004) Laboratory and CAIAC (2010) R&D Center, being active in embedded systems, microelectronics and organic electronics.
